Ignore I/o count when syntheis and implementation on vivado

Question

I have a design that contains a lot of io so they are more than the io of the fbga My design will be connected to a top level module But for now I want to syntheis that without connecting the design IOs to fbga bins

I want the input out signals not to be connected to the fbga bins in the synthesis — A_S, Jul 23 '18 at 20:42
The design is a cpu core it has a lot of io signals So it's more than the fbga can hold The module will be connected to another module later but for now I want to synthesis it to test the timing and so on But I cannot because it has too many inputs more than the fbga has — A_S, Jul 23 '18 at 20:44
"But I cannot because it has too many inputs more than the fbga has" Where does that come from? Have you tried? — Oldfart, Jul 23 '18 at 20:58
How about creating a wrapper module around your CPU with only selected IOs? — wahab, Jul 24 '18 at 08:58

score 0 · Answer 1 · answered Jul 24 '18 at 12:59

What you're describing is out-of-context mode. That allows you to synthesize a module with all the IO as virtual pins.

You can set it through the GUI as described on page 20 here: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2013_1/ug901-vivado-synthesis.pdf

Or using the TCL command:

set_property -name {STEPS.SYNTH_DESIGN.ARGS.MORE OPTIONS} -value {-mode out_of_context} -objects [get_runs synth_1]

Ignore I/o count when syntheis and implementation on vivado

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