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Questions tagged [vivado]

Vivado® Design Suite is a development environment published by Xilinx for designing with their FPGA devices.

The Xilinx Vivado® Design Suite delivers a SoC-strength, IP-centric and system-centric, next generation development environment that has been built from the ground up to address the productivity bottlenecks in system-level integration and implementation. The Vivado Design suite is a Generation Ahead in overall productivity, ease-of-use, and system level integration capabilities.

http://www.xilinx.com/products/design-tools/vivado.html

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Vivado SDK doesn't recognize the functions inside #include "math.h"

I wrote a simple project in Vivado SDK in order to test my HW-platform developed in Vivado. My problem is that the SDK doesn't recognise the sin() function. I've included the "math.h" library without any error, the program recognise the library…
Arturete
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Why do we use REG in FGPA / VHDL / VIVADO?

I am programming with Xilinx's vivado in verilog. I was wondering why for some outputs we use reg For example reg [3:0] encoder_output we use that because our 16 to 4 encoder has 4 outputs right? I am assuming that we use reg whenever we need to…
Kenny Truong
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Error synthesizing hierarchical names in vivado

Using Vivado 2015.1, I'm attempting to use a hierarchical name to access an object on the top level module of my design. The simulation runs fine but I receive the following synthesis error: [Synth 8-660] unable to resolve 'top'…
jwanga
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Vivado_hls 2014.4 Ubuntu 14.04 x64 vivado includes error

I am running Vivado HLS 2014.4 (x64) on Ubuntu 14.04 x64. Everything works in Vivado HLS 2012. In Vivado HLS 2014.4 GUI and Synthesis works but compilation of testbench does not. I am getting thousands of errors like this: Building file:…
Nic30g
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Add library to Vivado 2014.4

I am quite new to Vivado and VHDL and I would like some guidance on a fundamental issue. I am guessing that I can create my own libraries and use them in my projects as i do with the default and fundamental ones eg: library IEEE; use…
Rizias
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Run all TCL scripts in a folder

I have a folder with many TCL files, and I need to run them all (in Vivado). How can I save time in running all of them at once? Is there something as easy as: source [path/]*.tcl ?
AryT
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Inline assemble(riscv32) in C

I try to realize inline assemble(riscv32) command in one program C and use litex to create the project in vivado and generate bin file. In simulation, part ASM does work (memory position x'10000400 does have value x'40) but when I implement in card…
KabiLink
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Passing parameters between Verilog modules

I fairly new to Verilog and learning the ropes. I have some code which generates an 8 bit up-counter (module counter.v), which is then called by a top module (top_module.v). There is a simulation test fixture (test_fixture.v) which calls the top…
McKendrigo
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VHDL: formal port 'portName' has no actual or default value

I receive a compilation error on VHDL test bench instantiating VHDL module PWM: "formal port 'Duty_Cycle' has no actual or default value". The error is seen when standing on "dev_to_test: PWM" line of code. In instantiated PWM module the Duty_Cycle…
chainastole
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How to start "Xilinx SDK" from command line instead of from Vivado "File->Launch-SDK" Menu?

I'm wondering how to start "Xilinx SDK Eclipse GUI" (XSDK) directly from the command line? Currently, I'm launching XSDK by first launching "vivado", and then going to the "File->Launch SDK" menu. However, this is a bit cumbersome to always open…
Bimo
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Vivado: Warning The clock pin x_reg.C is not reached by a timing clock (TIMING-17)

I'm trying to compile some FPGA code using Xilinx's Vivado tool. However, when I run "Synthesis" and then select "Report methodology"...I get the following list of Bad Practices: TIMING-17 TIMING #1 Warning The clock pin last_anthony_reg.C is not…
pico
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VHDL: Correctly way to infer a single port ram with synchronous read

I've been having this debate for years... What's the correct why to infer a single port ram with synchronous read. Let's Suppose the interface for my inferred memory in VHDL is: library ieee; use ieee.std_logic_1164.all; use…
pico
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vivado block designer not updating RTL interface in block design after modifying verilog or vhdl RTL files

I would swear that vivado has a bug in that it never refreshes any interface changes made to an RTL file, verilog or vhdl, after it has been pasted into the "block design" with "add module".... What the secret to get Vivado block designer to see…
pico
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GHDL simulator doesn't support vhdl attributes without error?

I wrote some vivado RTL and then added some vhdl attributes to the ports of the entity to define the interface to Xilinx Vivado tool as follows: library ieee; use ieee.std_logic_1164.all; entity vivado_rtl_island is port( -- Clocks …
pico
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Xilinx, Zynq, AXI4 interconnect. What are the performance implications of configuring register slice and data fifo options?

Consider an AXI4 Interconnect on the PL (FPGA) side. When I double click to see the available options, there is a tab in Slave interfaces. Containing the following options. What is the purpose of enabling register slice? Does outer refer to the…
CJC
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