Questions tagged [iverilog]

`iverilog` is a compiler that translates Verilog source code into executable programs for simulation, or other netlist formats for further processing.

iverilog is a compiler that translates Verilog source code into executable programs for simulation, or other netlist formats for further processing. The currently supported targets are vvp for simulation, and fpga for synthesis. Other target types are added as code generators are implemented.

Official site: http://iverilog.icarus.com
Source code: https://github.com/steveicarus/iverilog
Wikipedia

176 questions

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My Verilog code is compiling without any error - it is showing "vcd file opened for output" but after that no output is coming

Where is the problem occurring in my Verilog code? Design: module updown(q,clk,rst,up); output [3:0] q; input clk , rst , up; reg [3:0] q; always@ (posedge…

verilog system-verilog iverilog

asked Aug 06 '21 at 08:21

Vaani_005

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Assign inout to inout (SystemVerilog)

I need make I2C mux inside FPGA. SCL signal from master to slaves should be connected through mux and it's no problem. What about SDA signal? It should work in both directions. Directly connection without High-Z or clock synchronization. assign…

verilog system-verilog iverilog

asked May 12 '21 at 11:28

Vladislav Maier

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Verilog error handling two posedge signals in "always" block

I have a problem with an "always" block in Verilog. First let me present the code: module syncRX(clk, signal, detect, output clk_1khz); input clk, signal; output reg [7:0] detect = 0; //wire clk_1khz; freq_div div(.clk(clk),…

verilog fpga iverilog

asked Aug 22 '20 at 11:16

Carlos J.

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verilog AND gate when 32 not working correctly

The AND gate module andgate #(parameter Port_Num = 2, parameter WIDTH=8) ( input [(WIDTH-1):0] a, input [(WIDTH-1):0] b, input [(WIDTH-1):0] c, input [(WIDTH-1):0] d, input [(WIDTH-1):0] e, input [(WIDTH-1):0] f, input [(WIDTH-1):0] g, …

verilog iverilog

asked Jun 11 '20 at 01:20

Kearney

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1 answer

"error: Enable of unknown task": What does it mean in iverilog?

I googled the error, but I found nothing useful. The Verilog code: `timescale 1us/1ns module ShadyModule; reg [3:0] num1,num2; reg [4:0] res; `include "ShadyTask.v" initial begin num1 = 5; num2 = 10; $monitor ("num1= %d,…

verilog iverilog

asked Dec 16 '19 at 21:04

Adham Nour

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Assertion Failed Error Trying to compile SV files with Icarus

I tried compiling a mux.sv design module with its testbench using Icarus but I am getting the following error vvp: array.cc:906: void compile_var2_array(char*, char*, int, int, int, int, bool): Assertion `0' failed. Aborted (core dumped). Below is a…

verilog system-verilog iverilog icarus

asked May 09 '19 at 10:48

user2987773

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4 bit S R latch in verilog

I am writing verilog code for 4 bit S R latch. I have considered the latch to be asynchronous. So I have not included the clock. At first I have written code for 1 bit S R latch then I have used that code for 4 bit S R latch. module srlatch (S, R,…

verilog hdl iverilog

asked Sep 03 '18 at 09:10

Subhadip

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2 answers

Verilog behavior of IF statement with invalid value in condition

If IF-statement in Verilog has invalid value in condition, only else branch is evaluated. (In simulation.) For example below in module SimpleIfStatement2b if a = 1'bx: b=0'b1 I was searching in Vegilog-2005 standard for this behavior and and can not…

verilog fpga systemc iverilog

asked Feb 25 '18 at 16:42

Nic30g

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1 answer

I don't understand what is the syntax error in my iverilog

I write the code like this: module alu(input[7:0] a,input[7:0] b,input [2:0] op,output reg [7:0] y); always@(a or b or op) begin case(op) 3'b000: y = a + b; 3'b001: y = a - b; 3'b010: y = a * b; 3'b011: y = a / b; 3'b100: y = a & b; …

verilog iverilog

asked Aug 03 '17 at 17:48

Chi Chau Bo

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2 answers

Verilog: Sequential Block Time

Why is the time for all instructions in a sequential block (non-parallel) all the same? i.e. module abc; reg [31:0] r; initial begin r = 0; $display($time, " ", r); r = 1; …

time verilog iverilog

asked Jun 19 '17 at 23:06

NoName

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verilog declaring a not wire

Trying to declare a wire to be the opposite of wire C, we use nC for this wire. module lab_4 (A,B,C,D,E,Y); output Y; input A; input B; input C; input D; input E; wire A; wire B; wire C; wire D; wire E; wire nA; wire nB; wire nC; wire…

verilog iverilog

asked Feb 27 '17 at 06:57

Patrick D

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2 answers

how to re-write this code using generate statement?

I have a Verilog code which looks something like this. module top ( . . input a_2; input a_1; input a_0; ); bottom I_bottom( . . .a(a_2); ); …

verilog system-verilog iverilog

asked Jul 06 '16 at 05:18

user2956338

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1 answer

How to make a generic NxM signed array multiplier using verilog?

I did a 8 bit by 8 bit before,but it was not generic. i cant figure out how to adjust the code to make it NxM bit . can anyone help me?

verilog system-verilog iverilog

asked Apr 01 '16 at 15:05

Omar Magdy

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1 answer

Verilog module for ALU but doesn't work properly

I am trying to write down ALU for verilog. And there are several error I experiences. First of all, here is my code: module yAlu(z, ex, a, b, op); input [31:0] a, b; input [2:0] op; output [31:0] z, ztemp; output ex; wire[31:0]a0,a1,a2,a3,a4,…

verilog iverilog

asked Mar 21 '16 at 04:33

online.0227

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1 answer

How to do matrix multiplication in Verilog?

I am trying to multiply 1x3 * 3X64 matrix, here since each value in matrix is decimal number so for each value I have taken 4 bits that is 4x64 bits in total accessing 4bits of each row at a time. I tried to generalize it. The matrix is of form 1x3…

verilog fpga hdl asic iverilog

asked Mar 04 '16 at 06:59

Swaroop

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