Questions tagged [iverilog]

`iverilog` is a compiler that translates Verilog source code into executable programs for simulation, or other netlist formats for further processing.

iverilog is a compiler that translates Verilog source code into executable programs for simulation, or other netlist formats for further processing. The currently supported targets are vvp for simulation, and fpga for synthesis. Other target types are added as code generators are implemented.

Official site: http://iverilog.icarus.com
Source code: https://github.com/steveicarus/iverilog
Wikipedia

176 questions

-1

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3 answers

Array Declaration and Access Verilog

I am trying to create a 32 bit array with 10 spaces in Verilog. Here is the code: reg [31:0] internalMemory [0:9]; I then try to assign 32 bit values to different locations inside that register. Here is a code sample: internalMemory[0] =…

asked Apr 15 '15 at 04:46

Wilo Maldonado

-2

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1 answer

Missing close quote of string. Verilog

im creating a 16 bit ripple carry adder using verilog and simulate it using icarus but below i just have the test bench file attachment. Im new to learning verilog and i have this error code ("Missing close quote of string") that i cant seem to…

verilog iverilog

asked Dec 17 '22 at 08:14

Jak

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2 answers

what is wrong with the following code in verilog?

I am working on rs232 for over one week. My program takes a 13bit dataframe[from testbench] and serially transmits it. Now, I am testing the TX side. I think this[as commented below -here1, here2] is where the problem is. module…

verilog protocols hdl fsm iverilog

asked Sep 13 '21 at 11:01

SWETHA CHILVERI

-2

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1 answer

Why I can not copy a content of register to another one in "always" block in Verilog?

well, I have this code, that is working perfectly: module syncRX(clk, signal, detect); input clk, signal; output reg [7:0] detect = 0; reg [7:0] delay = 0; //wire clk_1khz; freq_div div(.clk(clk), .clk_1khz(clk_1khz)); …

verilog fpga yosys iverilog

asked Aug 22 '20 at 12:51

Carlos J.

-2

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2 answers

Module instantiation with the "number sign"

I have the main module with FIFO stuff. Here it is: module syn_fifo #( parameter DATA_WIDTH = 8, // inpit capacity parameter DATA_DEPTH = 8 // the depth of the FIFO ) ( input wire clk, input wire rst, //…

verilog iverilog

asked Jul 27 '20 at 15:03

sht4Bitch

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1 answer

Can parameters be variable

I know that we can use parameters to make generic modules, and to improve readability of code. My question is whether we can have these parameters themselves as a variable. Something like this: module parameterModule #(parameter p1, ...)(); …

verilog hdl quartus iverilog icarus

asked Jul 16 '20 at 03:11

Akilesh Kannan

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1 answer

Verilog Program when I compiler in VCS getting correct output but when I compiler in IVL getting different output

I am really confused. I did verilog programming and compiled and executed in VCS. It is giving correct values at expected clock cycles. When I run it is ivl32 it is giving slightly different values. I am confused completely. Can some one tell me…

verilog system-verilog iverilog

asked May 10 '16 at 07:33

vishnu prasanth

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2 answers

Verilog module cannot calculate a&b and a|b

I am creating the verilog module that calculate either one of a+b, a-b, a & b or a | b. The problem is that it does calculate for a+b and a-b. but it cannot calculate a & b and a | b and return nothing. input [31:0] a, b; input [2:0] op; output…

verilog iverilog

asked Mar 20 '16 at 05:48

online.0227

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1 answer

How to make an array in 'verilog' (code inside)

I want to make an array called 'a' and fill it with any binary numbers and It's 1-D array my code must do as sw in mips (store word) 'm' the value that I want to store it in 's' Thank you, module ALU(m,s,control,out,zeroflag,array); input [31:0]…

arrays verilog iverilog

asked Jan 01 '17 at 19:17

M.Sayel

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