-1

I googled the error, but I found nothing useful. The Verilog code:

`timescale 1us/1ns
module ShadyModule;
reg [3:0] num1,num2;
reg [4:0] res;
`include "ShadyTask.v"
initial
begin
    num1 = 5;
    num2 = 10;
    $monitor ("num1= %d, num2=%d",num1,num2);
    ShadyTask(num1,num2,res);
end


endmodule

The ShadyTask.v file contains:

task ShadyTask;
    input[3:0] num1,num2;
    output[4:0] sum;
    begin
        sum = num1+num2;
    end
endtask
toolic
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Adham Nour
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  • Does this answer your question? [Call task from another Verilog module](https://stackoverflow.com/questions/46837856/call-task-from-another-verilog-module) – toolic Nov 27 '22 at 14:37

1 Answers1

-1

I had the same problem and solved it based on this. Make sure ShadyTask.v isn't inside a module. If what you gave is the whole file it should work fine. But if it's

module ShadyTaskModule;
  task ShadyTask;
    input[3:0] num1,num2;
    output[4:0] sum;
    begin
        sum = num1+num2;
    end
  endtask
endmodule

that won't work.

DanielLC
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