My Verilog code is compiling without any error - it is showing "vcd file opened for output" but after that no output is coming

Question

Where is the problem occurring in my Verilog code?

Design:

module updown(q,clk,rst,up);

output [3:0] q;

input clk , rst , up;

reg  [3:0] q;

always@ (posedge clk)

begin

if(up==1)

begin

if(rst|q==4'b1111)

q<=4'b0000;

else

q<=q+4'b1;

end

else

begin

if(rst|q==4'b0000)                               

q<=4'b1111;

else

q<=q-1;

end

end

endmodule

testbench file

module tb_up_down;

reg clk,rst,up;

wire [3:0] q;

updown c1(q,clk,rst,up);

initial
 

begin

$dumpfile("tb_up_down.vcd");

$dumpvars(0,q,clk,rst,up);

rst=1;

up=0;

clk=1;

end

always #5 clk=~clk;

always #80 rst=~rst;

always #160 up=~up;

endmodule

output

after this it is taking no command

Answer 1

If you want to show something you should add $display to your testbench.

Your simulation is never ended, you can end it using a $finish, like this

initial begin
  #1000;
  $finish;
end