how to re-write this code using generate statement?

Question

I have a Verilog code which looks something like this.

module top (
    .
    .
    input a_2;
    input a_1;
    input a_0;
);
    bottom I_bottom(
                    .
                    .
                   .a(a_2);
                   );
    bottom I_bottom_2(
                       .
                       .
                       .a(a_2);
                      );
    bottom I_bottom_1(
                       .
                       .
                       .a(a_1);
                     );
    bottom I_bottom_0(
                      .
                      .
                      .a(a_0)
                     );
endmodule

How do I write this code using a generate statement? Please note that the inputs in top are fixed in top. I cannot change that to an array like a[2:0].

score 4 · Answer 1 · answered Jul 06 '16 at 05:57

Create vector to equate with the individual port wires. Then use generate and index the vector to get at each signal. This works equally for inputs or outputs.

You do have to build the vector manually, but there is no escape from converting somewhere due to the original requirement to keep the individual port names. At least it is done only once, and done succinctly.

module top (
    .
    .
    input a_2;
    input a_1;
    input a_0;
);

wire [4:0]vec_a = {a_4, a_3, a_2, a_1, a_0};
generate genvar i;
    for(i=0; i<5; i=i+1) begin
        bottom I_bottom(
                .
                .
               .a(vec_a[i]);
        );
    end
endgenerate

endmodule

jskroch · Answer 2 · 2016-07-11T22:01:21.293

1

Just to make explicit the suggestion @toolic made in a comment, you could write an array of instances like so:

module top (
    input a_3,
    input a_2,
    input a_1,
    input a_0
);

    bottom I_bottom[3:0] (
                      .a({a_3,a_2,a_1,a_0})
                     );
endmodule

Note that I've renamed your instance I_bottom to I_bottom[3] and connected it to input a_3, not a_2. I'm not sure if you intended to break the pattern there.

I realize that this doesn't answer the question as asked, as it doesn't use the generate statement. I think I like the solution that does use generate better.

edited Jul 11 '16 at 22:01

answered Jul 08 '16 at 21:54

jskroch

333
2
8

Neat trick! I did not realize you could do this. It is probably more confusing and less explicit when there are a lot of ports or ports are themselves buses. But for making arrays of simple instances or a lot of them, this method could be quite concise. Putting this in the toolbox in case I need it someday :) – Anders Jul 09 '16 at 04:12

how to re-write this code using generate statement?

2 Answers2