Questions tagged [iverilog]

`iverilog` is a compiler that translates Verilog source code into executable programs for simulation, or other netlist formats for further processing.

iverilog is a compiler that translates Verilog source code into executable programs for simulation, or other netlist formats for further processing. The currently supported targets are vvp for simulation, and fpga for synthesis. Other target types are added as code generators are implemented.

Official site: http://iverilog.icarus.com
Source code: https://github.com/steveicarus/iverilog
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176 questions

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1 answer

reg qb; cannot be driven by primitives or continuous assignment

I'm trying to make an SR flipflop on Icarus Verilog. Flipflop module: module srff(sr,clk,q,qb); input [1:0]sr; input clk; output reg q,qb; always@(posedge clk) begin case(sr) 2'b00: q=q; 2'b01: q=0; …

asked Nov 08 '22 at 17:43

Prerk

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2 answers

I get a warning about $readmemh: Too many words in the file

Here is how I define the rom module module rom( input wire [31:0] inst_addr_i, output reg [31:0] inst_o ); reg [31:0] rom_mem[0:100]; always@(*) begin inst_o = rom_mem[inst_addr_i>>2]; end endmodule Here…

verilog test-bench iverilog

asked May 10 '22 at 06:28

shikyeeee

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2 answers

I am trying use the output of a 16-bit encoder as to give input to the register (PIPO)

I am trying use the output of a 16-bit encoder as to give input to the register(PIPO). The 16-bit encoder will give 4-bit binary output; these 4-bit binary output will be given as input to the register. `timescale 1ps/1ps module encoder16to4…

verilog test-bench iverilog

asked Jan 04 '22 at 14:29

Sobebar Ali

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2 answers

How does verilog treat input values to if statements in always_ff blocks

I'm currently working on a pipelined MIPS cpu using Icarus Verilog and have come across some very strange behaviour when using an if statement within an always_ff loop. I'm currently testing this implementation of a PC block: module PC ( input…

verilog system-verilog iverilog

asked Dec 31 '21 at 00:24

Mineglitch

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1 answer

Error launching EPWave: [Could not parse file: $timescale not found in the header.]

I was trying to make a UART transmitter with baud rate 9600 on EDA playground using icarus verilog as my simulator. Here is my code: `timescale 1s/1us module UART_9600_8N1( output reg trans, input [7:0] bitsin ); reg [9:0] storagebits; reg…

verilog system-verilog iverilog

asked Dec 19 '21 at 10:38

KaBe2003

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2 answers

Error: Unable to assign to unresolved wires

I wrote a code for a bidirectional counter which works as an up counter if parameter updown=1 and down counter otherwise on EDAplayground using icarus verilog as my simulator: module upctr( output reg [3:0] num, input clock ); …

verilog system-verilog iverilog

asked Dec 19 '21 at 06:59

KaBe2003

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2 answers

What is ''_'' in Verilog?

I was viewing this code snippet: module FD2 (d, cp, cd, q, qn); input d, cp, cd; output q, qn; nand #1 nand_2 (n2, d_, cp_), nand_3 (n3, n1, n4), nand_7 (q, n5, qn); // SJM nand #0 nand_1 (n1, d, cp_, cd), …

verilog system-verilog iverilog

asked Jul 31 '21 at 17:51

SWETHA CHILVERI

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1 answer

Trying to simulate JK-FF with gate level code

I've been trying to simulate a JK-FF with gate level code, but it's not working. Any help is appreciated. Circuit code: module circuit1_3_c(j,k,r,cp,q,q1); input j,k,r,cp; output q,q1; wire…

verilog iverilog

asked Apr 19 '21 at 18:36

Abdur Rakib

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1 answer

alu.v:55: syntax: error: Invalid module instantiation and it say "I give up."

My ALU_1bit is right, and I had test it. But, my alu has problems. how should I fix it? alu.v:55: syntax error alu.v:55: error: Invalid module instantiation I give up. ALU_1bit code timescale 1ns/1ps module ALU_1bit( input src1,…

verilog iverilog

asked Mar 27 '21 at 20:07

sdragon

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1 answer

Test for a 8-bit full adder giving x instead of numbers

For a university class, we were told to do an 8-bit full_adder out of full_adders and a test. I believe the main code is correct, but I might have done some errors on the test. I would really appreciate if I could get some help with the x…

verilog iverilog

asked Mar 24 '21 at 19:27

GHG HGH

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1 answer

Problems running a test in Verilog

I was trying to run a testbench on Verilog, but I keep running into some problems. I added the errors at the end for y'all to see them. Here is the module: module combinational_logic( A, B, C, D, AnotCnotD, BCDnot, …

testing verilog system-verilog test-bench iverilog

asked Mar 04 '21 at 20:55

GHG HGH

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1 answer

I can't compile a .sv file (SystemVerilog)

I'm learning SystemVerilog for the university. I installed the extensions in Visual Studio Code for syntax highlighting: SystemVerilog, Verilog-HDL/SystemVerilog/Bluespec SystemVerilog (Names of extensions). I installed the compiler Icarus Verilog…

system-verilog iverilog

asked Jan 30 '21 at 14:11

Gabbed

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1 answer

What is this following syntax error in Verilog Icarus tool?

module alu(input [7:0] A,B, input [3:0] selector, output [7:0] ALU_output, output ALU_output_carry ); reg [7:0] ALU_result; wire [8:0] tmp; assign ALU_result=ALU_output; assign tmp={1'b0,A}+{1'b0,B}; assign…

verilog system-verilog test-bench iverilog

asked Jan 13 '21 at 12:10

MR LUN

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1 answer

Arbitrary Counter only displaying zeros

I have to make an arbitrary counter for a determined sequence, and after making the transition table and the karnaugh maps, I was left with some equations that I turned into this Verilog program. It uses four JK bistable circuits. However, when I…

verilog counter iverilog

asked Jan 09 '21 at 14:04

Pablo López

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1 answer

Invalid module instantiation

I am trying to take a floating point input and split it it into its sign, mantissa and exponent values. At lines 7 and 8, my compiler (I'm using Icarus Verilog) is giving the error: Invalid module instantiation even though I haven't instantiated…

verilog system-verilog iverilog

asked Dec 04 '20 at 11:31

Sandeep Daniel

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