Verilog error handling two posedge signals in "always" block

Question

I have a problem with an "always" block in Verilog. First let me present the code:

module syncRX(clk, signal, detect, output clk_1khz);
    input clk, signal;
    output reg [7:0] detect = 0;

    //wire clk_1khz;
    freq_div div(.clk(clk), .clk_1khz(clk_1khz));
    
    always @(posedge signal, posedge clk_1khz)
     begin
        detect <= detect + 1;
     end

endmodule // top

module freq_div(input clk, output reg clk_1khz);
    reg [12:0] count = 0;
    always @(posedge clk)
     begin
        if(count == 6000)
            begin
                clk_1khz <= ~clk_1khz;
                count <= 0;
            end
        else
            count <= count + 1;
     end
    
endmodule

I got this error message (using Icestorm):

2.3.7. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal \freq_div.\clk_1khz' using process \freq_div.$proc$syncRX.v:22$4'. created $dff cell $procdff$15' with positive edge clock. Creating register for signal \freq_div.\count' using process \freq_div.$proc$syncRX.v:22$4'. created $dff cell $procdff$16' with positive edge clock. Creating register for signal \syncRX.\detect' using process \syncRX.$proc$syncRX.v:8$1'. ERROR: Multiple edge sensitive events found for this signal! make: *** [Makefile:44: syncRX.bin] Error 1

I could detect that the "always" block involved is:

always @(posedge signal, posedge clk_1khz)
     begin
        detect <= detect + 1;
     end

becaise if change "always @(posedge signal, posedge clk_1khz)" for "always @(posedge signal)" works.

Also fails in that same way:

always @(posedge signal)
     begin
        detect <= detect + 1;
     end
    
    always @(posedge clk_1khz)
     begin
        detect <= detect + 1;
     end

And the error disappears when comment the line "detect <= detect + 1;" in bought of cases. Then the error is related to the access to the "detect" counter register. I have not idea why I can not trigger this counter from two different signals, but in fact, I have to increase the counter in bought post edge signals (and I can figure out in my mind a very simple digital circuit doing this), and I found many examples in Verilog using a "always" block with two posedges triggers... But mine dont works.

Please, if anyone can explain me why dont work and how I can do it. It will be extremely useful for me.

You are trying to create something which cannot be synthesized: a flop with two clocks. You need to explain your algorithm around the `detect` signal. The fact that you use `signal` as a clock looks very suspicious. What is the nature of it? How is it related to the clk? — Serge, Aug 22 '20 at 13:00
Thank for answer Toolic, well, this is an early stage of an algorithm, the idea is increase a counter in two cases, or signal or in clk_1khz, is not implemented yet but the objective is: Imagine that in signal came three 1 in a row, and the baud rate is 1KHZ, you can count how many 1 using the clk_1khz, but didnt get there, I am just stack to make this compile. — Carlos J., Aug 22 '20 at 13:20

Serge · Accepted Answer · 2020-08-22T19:59:29.417

1

I guess you can use separate counters for each clk_1khz and signal. Then just add them:

always @(posedge signal)
     begin
        detect_sig <= detect_sig + 1;
     end
    
always @(posedge clk_1khz)
     begin
        detect_clk <= detect_clk + 1;
     end

assign detect = detect_sig + detect_clk;

Though, @(posedge signal) looks strange to me. You should not use anything but clocks here. So, check your algorithm.

And, you should also simulate and verify your model before synthesizing.

Since you asked this in another question, your second variant with 2 different always blocks is not synthesizable either. It results in the detect signal driven by multiple always blocks and causing a multiply-driven condition in synthesis. In simulation it will cause non-deterministic results. synthesis should break. Check messages.

edited Aug 22 '20 at 19:59

answered Aug 22 '20 at 19:39

Serge

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Hi Serge, thanks for answer, well, I tryed your solution but stills chashing, seams the line "assign detect = detect_sig + detect_clk;" what is making the warning "Warning: No clocks found in design" and the FPGA dont react... Should be different solution. – Carlos J. Aug 23 '20 at 10:08
1

this is a different message than you had before. – Serge Aug 23 '20 at 14:58
Seams that I post my question in the wrong place... – Carlos J. Aug 24 '20 at 12:27
@CarlosJ. This is a nice answer. Seems like you should look up how to declare clocks for your environment. – Moberg Aug 25 '20 at 05:41
@Moberg, you are right, "detect" was declared as a register and that why I had the warning! – Carlos J. Aug 25 '20 at 15:55
@Serge, thanks for the solution, you were right, and sorry for my last comment, just got some sensibility because the reaction of my questions in the forum, anyway is not your fault. – Carlos J. Aug 25 '20 at 15:56

Verilog error handling two posedge signals in "always" block

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