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I tried compiling a mux.sv design module with its testbench using Icarus but I am getting the following error vvp: array.cc:906: void compile_var2_array(char*, char*, int, int, int, int, bool): Assertion `0' failed. Aborted (core dumped).

Below is a code snippet of the test bench

`include "mux.sv"
module tb_mux();

    bit a0, a1, a2, d0, d1, d2, d3, d4, d5, d6, d7, out;
    // read
    bit expectedOutput;

    int passedFile;
    integer i;
    bit [11:0] testvector[2047:0];

    // design unit under test instantiation
    mux dut(.out(out), .a0(a0), .a1(a1), .a2(a2), .d0(d0), .d1(d1), .d2(d2), .d3(d3), .d4(d4), .d5(d5), .d6(d6), .d7(d7));
initial begin
            $readmemb("testcases", testvector);
            passedFile = $fopen("passed.txt", "w");
            if(passedFile)
                $display("file opened");
            else
                $display("couldn't open the file");
end

task assertOutput;
    begin
    int unsigned cases = 0;
    for (i = 0; i< 2048; i++)begin
        {a0, a1, a2, d0, d1, d2, d3, d4, d5, d6, d7, expectedOutput} = testvector[i];

       #10;
           if(a0 == 1'b0 && a1 == 1'b0 && a2 == 1'b0 && out == expectedOutput)
                cases = cases + 1;

           else if(a0 == 1'b0 && a1 == 1'b0 && a2 == 1'b1 && out == expectedOutput)
               cases = cases + 1;

           else if(a0 == 1'b0 && a1 == 1'b1 && a2 == 1'b0 && out == expectedOutput)
               cases = cases + 1;

           else  $display(0);
    end
    $fdisplay(passedFile, "%d", cases);
end
endtask

endmodule

What could be wrong with my testbench for it to produce this error?

user2987773
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1 Answers1

-1

I had to change the bit data type to logic to get it working with the Icarus.

user2987773
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