4 bit S R latch in verilog

Question

I am writing verilog code for 4 bit S R latch. I have considered the latch to be asynchronous. So I have not included the clock. At first I have written code for 1 bit S R latch then I have used that code for 4 bit S R latch.

 module srlatch (S, R, En, Q, Qc);
    input S, R;
    input En;
    output Q, Qc;
    reg Q,Qc;
  always@(*)
    begin
      if(En)
        begin
          Q  =  ~(R | Qc); 
          Qc =  ~(S | Q); 
        end
    end

endmodule



module srlatch4 (S, R, En, Q, Qc);
    input [3:0] S, R;
    input En;
    output [3:0] Q, Qc;


  srlatch s1(S[0], R[0], En, Q[0], Qc[0]);
  srlatch s2(S[1], R[1], En, Q[1], Qc[1]);
  srlatch s3(S[2], R[2], En, Q[2], Qc[2]);
  srlatch s4(S[3], R[3], En, Q[3], Qc[3]);


endmodule

What is the problem? It is not passing the test case i.e Q(t) = 0x0x, Qc(t) = 1010 and S = 1100, R = 0000, En =0, Q(t+1) = 0x0x, Qc(t+1) = 1010

score 0 · Answer 1 · answered Sep 03 '18 at 12:47

0

Due to use of always @(En) , your procedural block statements only will be executed when there is a change in En signal value.

You could have coded like in below manner.

module srlatch ( input S,
                 input R,
                 input En,
                 output reg Q,
                 output reg Qc);

always @(*) begin
  if (En) begin
    Q  =  ~(R | Qc); 
    Qc =  ~(S | Q); 
  end
end

endmodule : srlatch

And also there is an incorrect expression for S-R latch implementation in your code.

answered Sep 03 '18 at 12:47

Kerul Modi

1
1

I am getting the error "Invalid module instantiation" when I am instantiating srlatch in srlatch4 module? – Subhadip Sep 03 '18 at 13:15
You probably have a problem with the code that comes before the module instantiation. – dave_59 Sep 03 '18 at 14:53
Dont forget to put semicolon (;) after module instantiation. – Kerul Modi Sep 04 '18 at 10:22
@Kerul Modi Can you please point out the problem in my code? I have modified the code according to your suggestion. But it is not passing all the test cases? – Subhadip Sep 04 '18 at 17:54
@Kerul Modi Would you please check and tell me the problem? – Subhadip Sep 04 '18 at 17:58
@Subhadip, Would you please elaborate more about your testcase scenario? – Kerul Modi Sep 06 '18 at 11:56

4 bit S R latch in verilog

1 Answers1