How to do matrix multiplication in Verilog?

Question

I am trying to multiply 1x3 * 3X64 matrix, here since each value in matrix is decimal number so for each value I have taken 4 bits that is 4x64 bits in total accessing 4bits of each row at a time.

I tried to generalize it.

The matrix is of form 1x3 [2,4,3] &

3*64(64 decimal value in each row)

row 1[111111111111111111111111111111(64)]

row 2[11111111(8)22222222(8).....88888888(8)]

row 3[1234567812345678..................12345678]

The code which I tried

always@(h1,h2,h3)
        begin
z1 =((w0[3:0]*h1[3:0])+(w1[3:0]*h2[3:0])+(w2[3:0]*h3[3:0]));
z2=((w0[3:0]*h1[7:4])+(w1[3:0]*h2[7:4])+(w2[3:0]*h3[7:4]));

.
.
.
.
.   
z64=((w0[3:0]*h1[255:252])+(w1[3:0]*h2[255:252])+(w2[3:0]*h3[255:252]));


    end

        endmodule

I need generalized form of this..

Error that I have got:

ERROR:HDLCompilers:110 - "mat.v" line 36 Least significant bit operand in part-select of vector wire 'h1' is illegal

for(i=3;i<255;i=i+4)
        begin
            for(j=0;j<255;j=j+4)

            begin
                z[i:j]=((w0[3:0]*(h1[i:j]))+(w1[3:0]*h2[i:j])+(w2[0]*h3[i:j]));

            end

score 0 · Answer 1 · answered Mar 04 '16 at 08:42

A part select in Verilog must have constant bounds. h1[i:j] is illegal. h1[i +: 4] is legal and means the same as the illegal h1[i:(i+3)]. (And h1[i+3 -: 4] means the same as the illegal h1[(i+3):i]).

However, wouldn't your problem not be better solved by using two dimensional arrays? eg:

reg [3:0] h1 [0:63];

How to do matrix multiplication in Verilog?

1 Answers1