Verilog module for ALU but doesn't work properly

Question

I am trying to write down ALU for verilog. And there are several error I experiences.

First of all, here is my code:

module yAlu(z, ex, a, b, op);

input [31:0] a, b;
input [2:0] op;
output [31:0] z, ztemp;
output ex; 
wire[31:0]a0,a1,a2,a3,a4, atemp;

assign slt = 0; 
assign ex = 0; 

assign a0 = a & b;
assign a1 = a | b;
assign a2 = a + b;
assign a3 = a - b;
assign a4 = a[31] ^ b[31];

yMux #(32) lo(zLo, a0, a1, op[0]);  
yMux #(32) hi(zHi, a2, a3, op[0]);
yMux #(32) temp(atemp, zLo, zHi, op[1]);
assign z = (op[2] == 1) ? a4 : atemp; 
assign slt = z;

endmodule

And yAlu.v uses following:

module yMux(z, a, b, c);
parameter SIZE = 2;
output [SIZE-1:0] z;
input [SIZE-1:0] a, b;
input c;
yMux1 mine[SIZE-1:0](z, a, b, c); // 2-­bit  2 -­to-­1  mux  and  it  would  be  cumbersome  to  write  32  mux  instantiation  lines.
endmodule

Lastly above yMux uses following:

module yMux1(z, a, b, c);
output z;
input a, b, c;
wire notC, upper, lower;
// Gates and interconnections for MUX

// if c is 0, z=a.
// if c is 1, z=b
not my_not(notC, c);
and upperAnd(upper, a, notC);
and lowerAnd(lower, c, b);
or my_or(z, upper, lower);
endmodule 

Here is is what it tests above yAlu:

module lab8;

reg [31:0] a, b;
reg [31:0] expect;
reg [2:0] op;
wire ex;
wire [31:0] z;
reg ok, flag;
yAlu mine(z, ex, a, b, op);

initial begin

repeat (10) begin

a = $random; b = $random;

if(op==0)
expect = a & b;
else if (op==1)
expect = a | b;
else if (op==2)
expect = a + b;
else if (op==3)
expect = a - b;
else if (op==4)
expect = (a < b) ? 1 : 0;

#1;

if(expect == z)     
$display("PASS : expected=%d, a=%d, b=%d, z=%d, op=%d", expect,a,b,z,op);

#1;

$finish;  
end 
end
endmodule

My questions in order as follow:

Question 1. 

Code above only works for 0 and 1. It doesn't work more than that. For example, on the 2nd source code, there is

a = $random; b = $random;

it doesn't work for this. it only works when a=1 or 0 and b=1 or 0.

Question 2. 

I am not sure "slt" function is working correctly. The instructor who teaches this never told me what slt does in lecture but have us design slt, by googling or something.

Question 3. 

Whenever I compile, i get following Error. Why is this?

    yAlu.v:38: warning: Port 1 (z) of yMux expects 32 bits, got 1.
    yAlu.v:38:        : Padding 31 high bits of the port.
    yAlu.v:39: warning: Port 1 (z) of yMux expects 32 bits, got 1.
    yAlu.v:39:        : Padding 31 high bits of the port.
    yAlu.v:40: warning: Port 2 (a) of yMux expects 32 bits, got 1.
    yAlu.v:40:        : Padding 31 high bits of the port.
    yAlu.v:40: warning: Port 3 (b) of yMux expects 32 bits, got 1.
    yAlu.v:40:        : Padding 31 high bits of the port.

I can't fix this at all.

I don't even know I am doing it correctly. The manual that directs me to do what it says has no enough explanation as well as no sample output.

I couldn't finish in time anyway, so I guess it doesn't matter but I think I have to know solution for my problems.

Thank you very much if you can help me out.

Answer 1

As shown by the warnings, your port connection width are mismatched. Refer to single warning and other are the same to tackle.

  yAlu.v:38: warning: Port 1 (z) of yMux expects 32 bits, got 1.
    yAlu.v:38:        : Padding 31 high bits of the port.

The module declares ports a,b,c and z, each of width defined by SIZE parameter.

module yMux(z, a, b, c);
parameter SIZE = 2;
output [SIZE-1:0] z;
input [SIZE-1:0] a, b;

Moreover, the SIZE is overridden while instantiating. Now, the value of SIZE is 32. Hence the width of each of a,b,c and z is 32-bits.

yMux #(32) lo(zLo, a0, a1, op[0]);  
yMux #(32) hi(zHi, a2, a3, op[0]);
yMux #(32) temp(atemp, zLo, zHi, op[1]);

Here, the ports zLo,zHi is not declared and used directly in port connection.

Referring to IEEE 1800-2012, section 6.10- Implicit declarations:

If an identifier is used in a port expression declaration, then an implicit net of default net type shall be assumed, with the vector width of the port expression declaration.

This, if an undeclared identifier is used as a connection to an instance then an implicit net is inferred.

Thus, zLo,zHi are implicitly declared as single bit nets and the rest 32-bits are padded with zeros. Just declare them as follows and all warnings shall be removed:

wire [31:0] zLo,zHi;

To get an error in such a situation, use default_nettype none compiler directive.

For more information, refer Sutherland SV Gotchas paper, section 2.2 and SystemVerilog IEEE 1800-2012 for implicit declarations.