Verilog: Sequential Block Time

Question

Why is the time for all instructions in a sequential block (non-parallel) all the same?

i.e.

module abc;
     reg [31:0] r;

     initial
          begin
               r = 0;
               $display($time, " ", r);
               r = 1;
               $display($time, " ", r);
               r = r + 2;
               $display($time, " ", r);
               $finish;
          end
endmodule

Output:

               0          x
               0          0
               0          2

plugwash · Answer 1 · 2018-11-23T20:34:48.367

2

Verilog is a language designed to describe models of hardware and test code for exercising those models that can be run in a simulator (it was later re-purposed as a language to describe hardware for logic synthisis tools).

"time" refers not to the real world the simulator is running in but to the simulated world inside the simulator. Roughly speaking time in the simulated world only moves forward when there is nothing left to do at the current time point.

edited Nov 23 '18 at 20:34

answered Jun 19 '17 at 23:41

plugwash

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Interesting, so this explains why a sequential block of code is not being reflected in its time unit. – NoName Jun 20 '17 at 02:15

score 1 · Accepted Answer · answered Jun 20 '17 at 00:34

Verilog description of hardware consists of procedural blocks. These blocks are executed in pseudo-parallel fashion relatively to each other. The code inside every block is simulated sequentially in the same time slot.

such procedural blocks are all 'alsways' blocks, initial block and final block. You are testing the initial block. It is special and is executed, as the name suggests, at the very beginning of the simulation. All statements sequentially and at time '0'.

for always blocks, the time will be non-zero, but still the same for all instructions in the same block.

If you want to see time differences in an initial block, you need to add delays, i.e.

initial
      begin
           r = 0;
           $display($time, " ", r);
           #1 
           r = 1;
           $display($time, " ", r);
           #1 
           r = r + 2;
           $display($time, " ", r);
           $finish;
      end

in the above example i added two 1-cycle delays. You should see the time incrementing in your case. Still all instructions are executed sequentially, the delay just stops execution for one cycle.

To see a parallel behavior you would need a real hardware description with always blocks and you need to simulate it for multiple cycles. Then you might notice that the order of prints between different always blocks will vary, depending on the state of the simulation. However even in this case simulator will finish simulation for all blocks for time 'a' before it starts simulation for other blocks for time 'b'.

"...simulated sequentially in the same time slot." Makes sense. I was wondering why we have the fork-join block if begin-end seems to run in parallel already. — NoName, Jun 20 '17 at 02:23
#1 in this case stops sequential execution of statements for 1 cycle. All statements after it will be executed in the next cycle. $time returns the number of executed cycles by default. — Serge, Jun 20 '17 at 09:45

Verilog: Sequential Block Time

2 Answers2