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Questions tagged [iverilog]

`iverilog` is a compiler that translates Verilog source code into executable programs for simulation, or other netlist formats for further processing.

iverilog is a compiler that translates Verilog source code into executable programs for simulation, or other netlist formats for further processing. The currently supported targets are vvp for simulation, and fpga for synthesis. Other target types are added as code generators are implemented.

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iverilog testbench module with outputs

I'm trying to make a testbench to simulate a working top level module (and child module) however I can't get iverilog to handle the output of top correctly (LEDS,RS232Rx and RS232Tx are physical pins) here's my attempt at a testbench module…
Chris Camacho
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BitSet Circuit in Verilog

A specific type of bit-level manipulation consists in setting or clearing one single bit in a multi-bit value, given its index and its new value. This operation can be implemented in hardware by a BitSet circuit with the following interface: Input…
dms94
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Ring Counter in Verilog

I need to modify this ring counter to shift from the most to least significant bit and then resets back to the most significant bit. The output should look like this: 100000 010000 001000 000100 000010 000001 100000 Ring Counter module…
Scruffy Nerfherder
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D Flip flop using JK flip flop and JK flipflop using SR flip flop

Hi was trying to write Both structural and Test bench code for D-flip flop using JK flip flop as well as JK-Flip flop using SR flip flop. but i was getting the some errors. Please anyone could help me out thanks in advance. Here is my…
Shiva
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Errors in benchmark code

Flipflop structural code and test bench code I don't know where I have made a mistake. I am getting few errors in the output. `timescale 1ns/1ps module t_ff ( input clk,t,rst_n, output reg q); always@(posedge clk ,negedge rst_n) begin …
Shiva
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Ring Counters in verilog

I am trying to create a 4 bit counter using D flip flops in Verilog. I am following this diagram https://i.stack.imgur.com/XbRAv.png. I got the code for the individual D flip flop. The problem I am having is with D0 in the first clock cycle. I am…
pascal vikrama
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Connect 5-bit bus to 32-bit output bus

My design needs multiple multiplexers, all of them have two inputs and most are 32 bits wide. I started with designing the 32 bit, 2:1 multiplexer. Now I need a 5 bit, 2:1 multiplexer and I want to reuse my 32 bit design. Connecting the inputs is…
lkamp
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Verilog 4-bit up-down counter designed using negative edge triggered T flip flops

I'm very new to Verilog HDL and I have to code this 4bit up down counter. With the help of some reading on up-down counters and t flipflops, I already made the following code: module up_down_4bitcounter ( out, up_down, clk, data, reset ); //Output…
Freeda Suing
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How do i get the input and output names of Verilog module using scripts or tools?

is there a tool or script somewhere that allows me to parse Verilog files to obtain the names of the inputs and outputs of the module? i tried to look at iverilog and yosys but they do not seem to have this feature. i can write my own but i do not…
adrianX
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iverilog environment set up on macbook

I tried to make iverilog command s.t I can run verilog program on my Macbook Air. After few steps for installing the files, the tutorial told me to type: export PATH=~/bin:/usr/local/iverilog/bin It worked in terms of iverilog command, i.e, I can…
Rob Ye
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localparam / parameter with unpack array : icarus

I am trying to initilize unpack parameter. module dut #(parameter int arr[3]) ( input logic clk ); endmodule module main; int t[3]; initial begin t[0] = 0; t[1] = 1; t[2] = 2; end localparam int arr1[3] = t; //'{1,2,3}; localparam int A0 =…
nir
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SVerilog can't compile in VSCode

Here are the cods (1st one is the testbench and the second one the module) `timescale 1ns/1ps `include "not_example1.sv" module testbench; parameter BITS = 4; logic [BITS-1:0] s_in; logic [BITS-1:0] s_model_outs; not_example1 …
user331990
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Why is this line getting the error : Expecting a left parenthesis ( '(' ) [12.1.2][7.1(IEEE)]?

I have a Verilog code for a simple multiplier as shown below, which takes two 32-b inputs which are split into two (16-b MSB and 16-b LSB) and multiplied: parameter WordLen1 = 32, WordLen2 = 16; output [WordLen2-1:0] M; input clk; input signed…
priscilla
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Iverilog include file can't find and modules are missing

I write Makefile to compile my current project. But the including file and module in testbench can't be found. The error information makefile source list It will work if I put all the source files in the same directory. Command below
Vayne
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Are recursive functions in Verilog synthesizable?

Functions which do not contain any delay assignments are synthesizable, hence all synthesized functions are combinational in nature. Will the function still remain synthesizable if we have a recursive call? Taking an example of Factorial function…
j_robot
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