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Questions tagged [iverilog]

`iverilog` is a compiler that translates Verilog source code into executable programs for simulation, or other netlist formats for further processing.

iverilog is a compiler that translates Verilog source code into executable programs for simulation, or other netlist formats for further processing. The currently supported targets are vvp for simulation, and fpga for synthesis. Other target types are added as code generators are implemented.

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How do I measure time between two markers in gtkwave?

I am simulating my verilog design using iverilog and dump the output to an fst file. I am then using gtkwave to view the waveform. gtkwave allows me to add a number of markers. How do I then measure the delta between any two markers. I read through…
Prashant
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How to include files in icarus verilog?

I know the basic `include "filename.v" command. But, I am trying to include a module which is in another folder. Now, that module further includes other modules present in the same folder. But, when I try to run the module on the most top-level, I…
Harshit Gupta
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Arithmetic shift by $signal give different result in conditional expression and always block

I'm writing ALU for MIPS. I used to write it as a sequential logic (or a always block? I don't know why but c must be a reg so I guess it's a sequential logic?) It seems to be combinational logic always @* begin case (op) 4'b0000: c =…
Yangff
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How to get synthesizable delay in verilog

I have done a error control code in verilog, in that I got decoded data with some delay of 18000 ns. I need to compare the decoded data with the original data but my original data start some 100 ns, so how to do comaparision of this two signals. How…
meghana MN
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Verilog Oracle, Expected Value doesn't work properly

I am fixing some problem of source code below. I am creating oracle that compare expected value to actually value I get. the expected value that I try to calculate is variable 'e'. and the actual value that I get is variable 'z'. so, variable 'ok'…
online.0227
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Verilog code compiles without error but no output

module encoder (op, in, clock, reset); //$display("We are in initial procedural block"); input [15:0] in; input clock, reset; output [3:0] op; wire [15:0] in; wire clock, reset; reg [3:0] op; always…
user3043882
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How to concatenate strings in Icarus Verilog?

I have a SV printing task that concatenates some input strings and prints a message. This code works on Cadence's tools, but when I tried porting to iverilog, I get compile errors. task Error ( input string msg, input string name…
meteowrite
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Error: 'a' has already been declared in this scope

I have made two files (or_gate and or_gate_tb) in vscode, and I am trying to run using the following command on the macOS terminal: iverilog -o or_gate.vvp or_gate_tb.v This is my result, and I can not find anything wrong with my…
verilognewbie
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How to print output and create a .vcd file?

I am a beginner, and I am learning VerilogHDL. I am trying to implement a simple NOT GATE code. What I want to do is print the output of the simulation with the $monitor() function, and I want to generate a .vcd file to be able to simulate it with…
Mahmoud Abdel-Rahman
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How to cancel address comment by $writememb?

When I use $writememb in Verilog to write contents in a memory to a text file, the result shows as below. But, I don't need the address comment. How can I cancel the comment when using $writememb? I use iverilog to compile my design. //…
flyxia624
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Does iverilog support "int unsigned" of SystemVerilog?

I tried to simulate cvfpu(a floating-point unit written in SystemVerilog) with iverilog, but the compiler gave up every time when there was parameter int unsigned in source code even if I added -g2005-sv. Does it mean that int unsigned is not…
Ibroad
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Error: "Syntax in assignment statement l-value." while trying to assign a reg inside an always block

I'm trying to model a circuit. Here is the code of the circuit I'm trying to build. I get the error inside the always block and specifically inside the cases. I'm trying to assign reg NextState to a specific state; however I get an error. module…
Dimitris Papadimitriou
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icarus verilog: Unable to bind variable

I am trying to pass a string as parameter to a module and getting this error: Unable to bind variable module dut #(parameter string CONFIG_FILE) ( input logic clk ); endmodule module main; localparam string CONFIG_FILE = "Config.txt"; logic…
nir
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The waveform of the signal does not change

For my code, I want if the register 'gen_reg1' is not empty, the flag 'reg_file_empty' is set to 0. If the 'gen_reg19' is not empty, the flag 'reg_file_full' is set to 1. But the waveform is not changing as I want. I just wonder how to fix…
Shibo Dang
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Can I assign a value to an integer with the help of another integer?

I'm working on a Verilog module where I want to add a clock that is able to be changed through frequency values. I tried referencing two variables as integers, assigned the first variable [frequency] a number that corresponds to the frequency value…
teach_me
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