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Questions tagged [yosys]

Yosys is an open-source framework for (Verilog) HDL synthesis and formal verification. It is highly customizable using scripts and a C++ extensions API.

Yosys is an open-source framework for (Verilog) HDL synthesis and formal verification. It is highly customizable using scripts and a C++ extensions API.

180 questions
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Yosys optimizes away ring oscillator on ice40 FPGA

Im trying to implement a simple ring oscillator for an ice40 FPGA using yosys (0.7) as follows: module ringosc(input clkin, output out); (* keep="true" *) wire [100:0] ring; assign ring[100:1] = ~ring[99:0]; …
farindk
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Yosys logic loop falsely detected

I've been testing yosys for some use cases. Version: Yosys 0.7+200 (git sha1 155a80d, gcc-6.3 6.3.0 -fPIC -Os) I wrote a simple block which converts gray code to binary: module gray2bin (gray, bin); parameter WDT = 3; input [WDT-1:0] gray; output…
EEliaz
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Primitives in Yosys

I am using YOSYS to convert Verilog to BLIF. Input is a circuit (L_0_0) that only contains not, and, or primitives and some behavioral latching code. Here is my Verilog code The commands I use are: > read_verilog > proc; opt; memory; opt;…
Laleh
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Is it possible to remove clock input variable from the AIGER output?

Consider the example: read_verilog ./tests/simple/fsm.v synth -flatten -top fsm_test abc -g AND write_aiger -ascii -symbols hoho.aag The resulting AIGER file contains input variable clk, which is dangling. Is it possible to avoid introducing such…
Ayrat
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Constraints(Time/area..) in Yosys and/or ABC

I am using the following basic script to synthesize simple adder design # read design read_verilog fulladder1.v hierarchy -check # high-level synthesis proc; opt; fsm; opt; memory; opt # low-level synthesis techmap; opt # map to target…
Emin Aytac Derelioglu
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Extending existing cell libraries

I'm trying to create my own cell library in order to customize the mapping process. Does anyone have any idea on how to include a new cell library in the tool?
AbdelAziz
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Analyzing bitstreams using Icestorm

I'm trying to understand the bitstreams generated by Yosys/arachne-pnr as described on http://www.clifford.at/icestorm/: The recommended approach for learning how to use this documentation is to synthesize very simple circuits using Yosys and…
rlutz
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How do I get multi-bit ports to work in Yosys when the module is BLIF?

I cannot figure out how to get separate synthesis of modules to work in Yosys. Consider this simple two-module example: bottom.v module bottom(x, out); input [0:7] x; output [0:7] out; assign out = x+1; endmodule top.v module top(x,…
Sami Liedes
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Combinatorial synthesis: Better technology mapping results

Using the following script, I am synthesising to a standard cell library for which I have a lib file, my_library.lib: read_liberty -lib my_library.lib script yosys_readfiles.ys proc; opt; memory; opt; fsm -norecode; opt techmap; opt dfflibmap…
FriendFX
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Yosys : Is it possible to generate " Gate-level constraints file" using Yosys. That is like sdc file generated by Synopsys RTL compiler

Yosys: I am new to Yosys. But I am familiar with the RTL compiler. I am able synthesis modules using yosys. Is it possible to generate " Gate-level constraints file" using Yosys. That is like sdc file generated by Synopsys RTL compiler.
Sudheer Vaddi
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How to partition a top module into 2 sub-module using submod command?

I am having problem partitioning my top module using using submod command. I have a simple counter (I have a behavioral code for a 4bit counter). with the following cells in it: yosys> select…
Mehrdad
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How do I get a list of unconnected cell ports using the Yosys RTLIL API?

For a larger project, I need to create a list of unconnected cell ports using the Yosys RTLIL API. What is the best strategy for doing so?
CliffordVienna
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Can/does SigMap produce canonical output?

An instance of SigMap is guaranteed to produce the same output for every connected wire in a design. But does this hold true for different instances of SigMap running in different versions of yosys across different platforms? What about if the…
Jeremy Salwen
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How does the Yosys ConstEval API work?

I'm trying to write a plugin that requires evaluating combinatorial circuits. From what I can gather ConstEval is the tool which does this. However, the API is not so clear to me. Is there somewhere a rundown of the members of ConstEval and what…
CliffordVienna
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sequential RTL to combinational gate netlist

I have a dataset of RTL benchmarks, I was wondering if it is possible to convert a sequential RTL to a simple netlist with logic gates( AND, NOT, XOR. ..) instead of sequential components(FFs, latches.) I am looking to convert them into a binary…
gizen
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