Yosys logic loop falsely detected

Question

I've been testing yosys for some use cases. Version: Yosys 0.7+200 (git sha1 155a80d, gcc-6.3 6.3.0 -fPIC -Os)

I wrote a simple block which converts gray code to binary:

module gray2bin (gray, bin);

parameter WDT = 3;

input [WDT-1:0] gray;
output [WDT-1:0] bin;

assign bin = {gray[WDT-1], bin[WDT-1:1]^gray[WDT-2:0]};

endmodule

This is an acceptable and valid code in verilog, and there is no loop in it. It passes compilation and synthesis without any warnings in other tools. But, when I run in yosys the next commands:

read_verilog gray2bin.v
scc

I get that a logic loop was found:

Found an SCC: $xor$gray2bin.v:11$1
Found 1 SCCs in module gray2bin.
Found 1 SCCs.

The next code, which is equivalent, pass the check:

module gray2bin2 (
    gray,
    bin
);

parameter WDT = 3;

input [WDT-1:0] gray;
output [WDT-1:0] bin;

assign bin[WDT-1] = gray[WDT-1];

genvar i;
generate
    for (i = WDT-2; i>=0; i=i-1) begin : gen_serial_xor
            assign bin[i] = bin[i+1]^gray[i];
    end
endgenerate

endmodule

Am I missing a flag or synthesis option of some kind?

score 3 · Accepted Answer · answered Jun 30 '17 at 12:36

3

Using word-wide operators this circuit clearly has a loop (generated with yosys -p 'prep; show' gray2bin.v):

You have to synthesize the circuit to a gate-level representation to get a loop-free version (generated with yosys -p 'synth; splitnets -ports; show' gray2bin.v, the call to splitnets is just there for better visualization):

answered Jun 30 '17 at 12:36

CliffordVienna

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Thank you for the quick response! I'm not sure it helps though - The main interest for me is the FV feature of Yosys. The SMT2 backend give an "ERROR: Found logic loop in module" message. Is it even possible to deliver a netlist to the SMT backend? – EEliaz Jun 30 '17 at 14:05
I've checked it - running `synth; splitnets -ports` before `write_smt2` works, and the SMT tool doesn't give ERROR message. Thanks! – EEliaz Jun 30 '17 at 14:23
One issue gets fixed, and another pops up :) after running `synth; splitnets -ports` the `write_smt2` doesn't give ERROR message. But, before adding those lines the BMC found a counter example, but now it doesn't (and ends very fast). So I'm guessing I can't use the "synth" before `write_smt2`, right? – EEliaz Jun 30 '17 at 14:35
If your design has hierarchy then splitnets can break it. As I've said I've only included it above script to create a nicer schematic. There should be nothing that prevents write_smt2 to work with the output of `synth`. If there is a problem you should create another question for that and be sure to include the code and scripts necessary to reproduce the issue. – CliffordVienna Jun 30 '17 at 14:49

score 0 · Answer 2 · answered Jun 30 '17 at 17:12

The answer given by CliffordVienna indeed gives a solution, but I also want to clarify that that it's not suitable to all purposes.

My analysis was done for the purpose of formal verification. Since I replaced the prep to synth to solve the falsely identified logic loops, my formal code got optimized. Wires which I've created that were driven only by the assume property pragma, were removed - this made many assertions redundant. It's not correct to reduce any logic for the purpose of behavioral verification.

Therefore, if the purpose is to prepare a verification database, I suggest not to use the synth command, but to use a subset of commands the synth command executes. You can find those commands under: http://www.clifford.at/yosys/cmd_synth.html

In general, I've used all the commands specified in the above link that do not optimize logic:

hierarchy -check
proc
check
wreduce
alumacc
fsm
memory -nomap
memory_map
techmap
abc -fast
hierarchy -check
stat
check

And everything works as expected.

Yosys logic loop falsely detected

2 Answers2