I have a dataset of RTL benchmarks, I was wondering if it is possible to convert a sequential RTL to a simple netlist with logic gates( AND, NOT, XOR. ..) instead of sequential components(FFs, latches.) I am looking to convert them into a binary decision graph but so need to either get rid of these storage elements or simply not generate them during synthesis(if possible).
I tried synthesis using Yosys using different cell libraries.
