Primitives in Yosys

Question

I am using YOSYS to convert Verilog to BLIF. Input is a circuit (L_0_0) that only contains not, and, or primitives and some behavioral latching code.

Here is my Verilog code

The commands I use are:

> read_verilog <file>
> proc; opt; memory; opt; techmap; opt;
> write_blif <file>

The output file contains $_DFF_PN0_ as a .subckt with no .model, so when I input this file to MVSIS, it ignores all the subckts.

How can I map this sub circuit to somewhat known by other tools?

.model L_0_0
.inputs clk rst ce ins
.outputs outs
.names $false
.names $true
1
.names $undef
.names outs r_out_1_0 ce $0\outs[0:0]
1-0 1
-11 1
.names r_out_2_0 w_out_2_0 ce $0\r_out_2_0[0:0]
1-0 1
-11 1
.names r_out_1_0 w_out_1_0 ce $0\r_out_1_0[0:0]
1-0 1
-11 1
.names r_out_0_0 w_out_0_0 ce $0\r_out_0_0[0:0]
1-0 1
-11 1
.subckt $_DFF_PN0_ C=clk D=$0\outs[0:0] Q=outs R=rst
.subckt $_DFF_PN0_ C=clk D=$0\r_out_0_0[0:0] Q=r_out_0_0 R=rst
.subckt $_DFF_PN0_ C=clk D=$0\r_out_1_0[0:0] Q=r_out_1_0 R=rst
.subckt $_DFF_PN0_ C=clk D=$0\r_out_2_0[0:0] Q=r_out_2_0 R=rst
.names r_out_0_0 r_out_1_0 w_out_0_0
1- 1
-1 1
.names r_out_2_0 r_out_2_0 w_out_1_0
1- 1
-1 1
.names r_out_0_0 ins w_out_2_0
1- 1
-1 1
.names r_out_0_0 w_in_0_0
1 1
.names r_out_1_0 w_in_0_1
1 1
.names r_out_2_0 w_in_1_0
1 1
.names r_out_2_0 w_in_1_1
1 1
.names r_out_0_0 w_in_2_0
1 1
.names ins w_in_2_1
1 1
.end

New output with sync reset is below. Verilog output ports are all connected and seems that they are connected in BLIF too.

# Generated by Yosys 0.7 (git sha1 61f6811, i686-w64-mingw32.static-gcc 4.9.3 -Os)

.model L_0_0
.inputs clk rst ins
.outputs outs
.names $false
.names $true
1
.names $undef
.names r_out_0_0 $false rst $0\outs[0:0]
1-0 1
-11 1
.names w_out_1_0 $false rst $0\r_out_1_0[0:0]
1-0 1
-11 1
.names w_out_0_0 $false rst $0\r_out_0_0[0:0]
1-0 1
-11 1
.latch $0\outs[0:0] outs re clk 2
.latch $0\r_out_0_0[0:0] r_out_0_0 re clk 2
.latch $0\r_out_1_0[0:0] r_out_1_0 re clk 2
.names r_out_0_0 r_out_1_0 w_out_0_0
11 1
.names ins r_out_1_0 w_out_1_0
1- 1
-1 1
.names r_out_0_0 w_in_0_0
1 1
.names r_out_1_0 w_in_0_1
1 1
.names ins w_in_1_0
1 1
.names r_out_1_0 w_in_1_1
1 1
.end

score 2 · Accepted Answer · answered Jun 21 '17 at 13:38

2

The BLIF file format does not support storage elements with asynchronous resets. Unfortunately you do not post the Verilog code you used as input, but from what you have posted it is obvious that your Verilog does contains such storage elements. ($_DFF_PN0_ is a Yosys internal cell type used to represent a positive-edge flip-flop with negative polarity asynchronous reset-to-zero. Yosys just outputs that cell as it is since there is no equivalent construct for that in BLIF.)

If you would like to use BLIF output then you'll have to avoid using asynchronous resets in your design. There is nothing Yosys can do here because this is a limitation of the BLIF file format.

If you do not want to change the HDL code, but are fine with converting the asynchronous resets to synchronous resets, then you can simply run techmap -map +/adff2dff.v after running proc.

answered Jun 21 '17 at 13:38

CliffordVienna

7,995
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Thank you. You are right. My reset was async. When I change it to sync or use the techmap command, the problem is solved. My new problem is that when I input this to T-VPACK, it say there are unconnected ports and generates error. Even opt cannot resolve it. Can you help me with that? Thanks in advance – Laleh Jun 21 '17 at 18:02
@Laleh I don't know anything about T-VPACK. Are there unconnected pins in your design? If so, Yosys does not throw them away as this would change the module interface. Unconnected inputs shouldn't hurt. If the problem is unconnected inputs I would consider this a bug in T-VPACK. If the problem is unconnected outputs I would recommend to simply drive them with a constant values in your HDL code. – CliffordVienna Jun 21 '17 at 20:19
Thanks for your reply. Reported unconnected port is output, but it is not actually unconnected. I have updated question to include my Verilog file and also new output of Yosys. – Laleh Jun 22 '17 at 08:41
@Laleh I think that question is better addressed at the VTR people considering that I don't know a thing about their tools. Does T-VPACK accept a BLIF logic circuit or does it need a netlist that's already mapped to the primitives of the target architecture? I don't know.. I'd try my luck creating a ticket at https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues – CliffordVienna Jun 22 '17 at 13:04
I didn't know about VTR. It solevd my problem. Now I can use ODIN to convert from .v to .blif and give it to VPR. Thanks – Laleh Jun 23 '17 at 05:51

Primitives in Yosys

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