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Questions tagged [yosys]

Yosys is an open-source framework for (Verilog) HDL synthesis and formal verification. It is highly customizable using scripts and a C++ extensions API.

Yosys is an open-source framework for (Verilog) HDL synthesis and formal verification. It is highly customizable using scripts and a C++ extensions API.

180 questions
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Yosys optimizes GPIO RX module away

I recently started playing with the iE40 icestick evaluation board. I encountered what I think is strange behavior: It seems that Yosys wants to optimizes away a module which takes a port connected to a RX gpio pin. IMO this should never happen as…
Cornelius Korinthia
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Getting "Warning: Driver-driver conflict" errors from yosys

I'm messing around with FPGAs and am running into some warnings that I sort of understand but don't know what's causing them. My understanding is there was a conflict of some kind and it is resolved but using a constant value. Though that will cause…
Justin808
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Yosys: how to remove useless internal wires

Assume I have the following verilog: module demo(input a, output b); wire c; assign c = ~a; assign b = c; endmodule I would like to generate a verilog where the wire c is removed. I tried this: read_verilog…
alex137
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BLIF outputed by yosys involves DFF, and the BLIF file cannot be read by ABC

I'm new to yosys and ABC for logic synthesis. I downloaded one design aes_core from opencores, and run the following script with yosys to map the design into blif: read_verilog ./designs/apbtoaes128/trunk/rtl/*.v hierarchy -check -top…
Pu Yuan
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Does operator of `[]` of std::map always put the new item into the first place of iterator?

Hi I've met a problem relating to iterator order of inserted values in std::map by operator []. The code is a github program in line 265: many_async_rules[rstval].insert(sync_level); The definition of the map is std::map
Shore
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why are SB_LUT4 and SB_DFF not being packed by nextpnr?

I added the yosys tag, though this question is probably more about nextpnr (which has no tag on this site). I'm using yosys with nextpnr-ice40 on the following file. When I dump the design with --post-route /path/to/nextpnr/python/dump_design.py (I…
Hammdist
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How to see the synthesized RTL in openlane?

I have just started learning openlane. I want to see the RTL synthesis using openlane similar to how we get in vivado RTL synthesis. I have gone through the documentation but could not find anything regarding the same.
Kruti Deepan Panda
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iceprog - Can't find iCE FTDI USB device with Alchitry CU

I'm trying to upload my build code to my alchitry-CU FPGA board threw apio using iceprog on windows. apio upload which then executes iceprog -d i:0x0403:0x6010:0 hardware.bin And the output is init.. Can't find iCE FTDI USB device (device string…
Lopfi
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Yosys AIG output format unclear

I would like to know the format for the AIG generated by the json -aig command Example output: "models": { "$xor:0:0:1:1:1": [ /* 0 */ [ "port", "A", 0 ], /* 1 */ [ "port", "B", 0 ], /* 2 */ [ "nport", "B", 0 ], …
InputBlackBoxOutput
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Yosys - ERROR: TCL interpreter returned an error: invalid command name "verilog_defaults"

I am trying to write a tcl script to read and synthesize a design. I used the following commands at the top of the tcl file and executed it with yosys -c filename.tcl. verilog_defaults -add -I I got the following error: ERROR:…
sammy17
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Yosys -- producing an electronic schematics from verilog

I know, how to use yosys compile a .dot file from a verilog .v file in order to graphically check the verilog design. I use a target like this in my makefiles: dot: yosys \ -p "read_verilog -sv -formal $(file_main).v" \ -p…
71GA
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Yosys -- compilation of .dot file suceeds, but viewer (xdot) can't preview it

I have two modules, each in sepparate verilog file. One file is double_shift_reg.v with the top module double_shift_reg: `include "./shift_reg.v" `default_nettype none module double_shift_reg(clk, shi, in, out); input wire clk; // Clock …
71GA
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Formal verification with yices -- broken pipe

I am trying to formally verify my verilog FPGA design led_walker.v. So I first synthesize it to an .smt2 file: ┌───┐ │ $ │ ziga > ziga--workstation > 001--led_walker--verification └─┬─┘ └─> yosys \ -p "read_verilog -sv -formal led_walker.v"…
71GA
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How to get .bench file from verilog file

Test.v is here: module test(input A, B, C, D, E, output Y); assign Y = ((A^B)&C)^(D&E); endmodule Firstly I get .blif file by yosys (I use mycells.lib because I want only simple gates in bench file): read_verilog test.v hierarchy -check -top…
Rafet Bayram
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How to provide mapping information of xilinx primitives during yosys synthesis

I am new to Yosys and I am trying to synthesize a design using xilinx primitives. I want to know if we can synthesize a design using xilinx primitives. If yes, then how do we provide the mapping information of these xilinx primitives during…
N1T1N
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