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Questions tagged [yosys]

Yosys is an open-source framework for (Verilog) HDL synthesis and formal verification. It is highly customizable using scripts and a C++ extensions API.

Yosys is an open-source framework for (Verilog) HDL synthesis and formal verification. It is highly customizable using scripts and a C++ extensions API.

180 questions
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Vivado doesn't recognize cell in EDIF file generated by Yosys

I'm attempting to use Yosys to generate an edif file that I then use with Vivado tcl scripting to generate a bitstream for an Artix 7 (xc7a15t) FPGA. However, Vivado seems to have trouble with a few of the cells in the edif file. When I use the same…
MattHusz
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Can LUT cascade be used simultaneously with the carry-chain in the iCE40 FPGAs by any tools?

I try to construct the following: CO | /carry\ ____ s2 ---(((---|I0 |------------ O +------+((---|I1 | …
Baard
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(icestorm) do pins not specified in the pcf stay high impedance

as the title, additionally how do you specify another voltage level for single ended in/output for example LVCMOS18 - I'm guessing alas its not as easy as just an extra verb in a pcf entry...
Chris Camacho
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How can I use multiple IP cores that both contain modules with the same names with Yosys

Consider a design with two IP cores ip1.v and ip2.v that each declare a (different) module with the same name. For example, the contents of ip1.v: module ip1 (input A, B, C, output X); wire T; mygate gate_0 (.I0(A), .I1(B), .O(T)); mygate…
CliffordVienna
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Can I avoid opt_merge from removing a BUF? (Yosys tri-state workaround)

I know yosys has limited tri-state support, but I'm looking for a possible workaround. The following circuit: module TBUF2 ( inout SALIDA1, inout SALIDA2, input OE, output C); assign SALIDA1=OE ? 1'b0 : 1'bZ; assign SALIDA2=OE ? 1'b0 : 1'bZ; wire…
Salvador E. Tropea
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Yosys gives syntax error on 2d interface

I get "syntax error" on 2D interface declaration in Yosys, even with the "-sv" flag. Is there a way to make Yosys accept the next syntax? module somename #( parameter WDT = 3, parameter CNT = 2 ) ( input [WDT-1:0] in_a [CNT-1:0], …
EEliaz
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How to assign RAM values in an initial block in Yosys?

I am trying to use an initial block to assign values to a read-only inferred RAM: module rom ( input clk, input [5:0] addr, output reg [15:0] data); reg [15:0] mem [0:63]; initial begin mem[0] = 1; mem[1] = 2; …
R.Miller
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Correspondence between iCE40 I/O blocks and package pins

Is the correspondence between the I/O blocks of an iCE40 FPGA and the pins of the package they drive documented somewhere? The I/O tile documentation of Project IceStorm gives a list of I/O blocks, and for each block where its IE and REN bits are…
rlutz
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How to map clock gate to tech library cell

I have the following clock gate in the design: module my_clkgate(clko, clki, ena); // Clock gating latch triggered on the rising clki edge input clki; input ena; output clko; parameter tdelay = 0; reg enabled; always @ (clki, ena)…
FriendFX
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iceprog .. Can't find iCE FTDI USB device (Linux permission issue??)

I recently installed yosys on Ubuntu 15.1 (32-bit Arm-7 machine) and I compiled my first small project for a Lattice ice40hx8k dev board. However, the programming stage fails with: iceprog counter.bin Can't find iCE FTDI USB device (vedor_id 0x0403,…
scd
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gate level parsing using yosys

I want to parse the following sequential gate level net list. And I expect that the output will give me the gate ordering ( port order) so I can do other computation on the code. I tried to do that using yosys command read_verilog s27.v. I was able…
Never too late
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Yosys Can't open include file

I am getting a Can't open include file error with yosys. Is there a command line argument to define include directories and/or is there a default directory it is looking for include files in?
old_timer
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Does yosys preserve port ordering?

Does yosys preserve the ordering of input/output ports for modules/cells? Is the ordering in the RTL guaranteed to match the ordering of the verilog when it is read/written? Will the ordering ever be changed "unexpectedly" by yosys?
Jeremy Salwen
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How to execute yosys passes from an LLVM pass?

I have been working with two programs llvm's opt and clifford wolf's yosys both have similar interfaces for passes.(they use shared libraries as optimization passes) I want to use certain data structures and functions from yosys.h to build a design…
rajashekar
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What is the most powerful FPGA that yosys / Project IceStorm will target?

I have written an integer RISC-V-64 CPU in verilog. It builds with Verilator and passes tests, so now I want to upload it to an FPGA. I am new to this FPGA world. I have a Zybo Zynq 7000 given to me by a friend, but getting the tools from Xilinx…
Daniel
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