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Yosys: I am new to Yosys. But I am familiar with the RTL compiler. I am able synthesis modules using yosys. Is it possible to generate " Gate-level constraints file" using Yosys. That is like sdc file generated by Synopsys RTL compiler.

Sudheer Vaddi
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  • Please check this [URL](http://stackoverflow.com/help)it will be useful to lift your content quality up – Willie Cheng May 26 '16 at 22:47
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    Please give a small example of a input to Yosys and the output you want to get. Simply referring to the behavior of a prohibitively expensive closed-source tool will not help explain what you want to the majority of the people who do not have access to that closed source tool. – CliffordVienna Jun 01 '16 at 11:29

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