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I'm trying to create my own cell library in order to customize the mapping process. Does anyone have any idea on how to include a new cell library in the tool?

AbdelAziz
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Here is an example project that maps to a library in liberty (.lib) format:

https://github.com/cliffordwolf/yosys/tree/master/examples/cmos

Cell library: cmos_cells.lib
Synthesis script: counter.ys

CliffordVienna
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  • How do I learn the exact syntax and semantics of the .lib files used here? Also, do I need to provide the .lib file with a matching Verilog design that implements each of the cells mentioned in the .lib file? Please provide me with any references that might help me better understand how this works. – AbdelAziz Sep 16 '17 at 20:59
  • @AbdelAziz Just google for "Liberty File Format" for more information. No you don't neet to provide verilog models of your cells, liberty files contain all the information required. – CliffordVienna Sep 17 '17 at 13:44