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Questions tagged [yosys]

Yosys is an open-source framework for (Verilog) HDL synthesis and formal verification. It is highly customizable using scripts and a C++ extensions API.

Yosys is an open-source framework for (Verilog) HDL synthesis and formal verification. It is highly customizable using scripts and a C++ extensions API.

180 questions
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Generate TIE cells with Yosys?

I am using Yosys to synthesise my RTL design which includes a couple of literal constants, such as tied output ports as in the following code: module my_module ( input a, input b, output c, output d); assign c = a & b; …
FriendFX
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How to write the verilog to force yosys / nextpnr to output a manually designed logic tiles

I want to create a very compact parallel to serial shift register. I have manually designed a logic tile. I want yosys/nextpnr to just do the routing between this tile and the io pins. I have design the code to use yosys primitive, but nextpnr fails…
E. Timotei
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Lattice iCE40 JTAG

I am new to FPGA and I am trying to get a working JTAG setup on Lattice iCE40 FPGA. The board I'm using is from Olimex and has iCE40-HX8K FPGA. I'm using urjtag as PC application and tried with DirtJTAG and USB Blaster clones as programmer (flashed…
JohnnySorocil
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How to run post-synthesis simulation with the IceStorm iCE40 FPGA flow

It is good design practice to not only verify Verilog designs with regular pre-synthesis (behavioral) simulation, but also using post-synthesis simulation. This is practically mandatory when debugging mismatches between simulation and hardware. How…
CliffordVienna
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Why does yosys renumber vector ports?

My top level verilog module declares signals for the four LEDs on the myStorm ice40 board, which are labelled "LED1-LED4". module top ( output [4:1] LED ); assign LED = 4'b1010; endmodule I use the same numbering in the .pcf file: set_io LED[1]…
R.Miller
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Yosys how to use the qwp command

Regarding Yosys QWP command to measure wire lengths. I tried the QWP command however I do need more info, I did not find documentation on it. I hope you can help me: QWP gives the following statistics: Number of edges: 94380 Total…
Yosi Ben-Asher
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modify iCE40 bitstream to load new block RAM content

My current iCE40 FPGA project includes an 8-bit (soft IP) microprocessor connected to a 4Kx8 RAM which is composed from 8 2Kx2 block RAMs. It would be useful to be able to load new programs (for the 8-bit micro) into the 4kx8 RAM without requiring…
scd
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iceprog - Can't find iCE FTDI USB device

I'm trying to upload a bitstream file to iCEblink40-LP1K Evaluation Kit with iceprog on Arch Linux. sudo iceprog setbit.bin Then it complains: Can't find iCE FTDI USB device (vedor_id 0x0403, device_id 0x6010). And lsusb shows only: Bus 001 Device…
Sirius Lee
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How to simplify compound assignments in yosys

I am trying to get yosys to synthesize my design to structural verilog for a tool which doesn't understand the syntax {A, B} to specify the concatenation of values A and B. So for example when yosys generates statements like assign C =…
Jeremy Salwen
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Logical synthesis of decoder into standard logical cells

I have a decoder defined in verilog as: module my_decoder( input [3:0] in, output reg[19:0] out ); always@(*) begin case (in) 4'd0: out= 20'd114912; 4'd1: out= 20'd114912; 4'd2: out=…
gudise
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Yosys: Multiple edge sensitivities for asynchronous reset

I am teaching myself verilog, bare with me. :) I have a clock line called enable coming from a clock divider I created. I also have a rst button on my devboard. I would like to modify the following code to react to rst button presses by turning off…
Neekon Saadat
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Why Yosys synthesis the sequential statement to constant

I have the Verilog statement below: module test (A,B, CLK); input A, CLK; output B; always@(posedge CLK) if(A) B <= 1'b1; endmodule I am expecting a register. However, after I synthesis it with Yosys, I got the result as…
Donghui Li
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Understanding the SB_IO primitive in Lattice ICE40

I am playing with cliffordwolf/picorv32 and am having some problem understanding the following snippet in picosoc (link to source): SB_IO #( .PIN_TYPE(6'b 1010_01), .PULLUP(1'b 0) ) flash_io_buf [3:0] ( .PACKAGE_PIN({flash_io3,…
nalzok
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Is there any way to get default parameter value for verilog module with Yosys

I am trying to get default parameter values for verilog modules using Yosys command shell. Is there any way to do it? In addition, is parsing a `write_ilang' command output file a good idea or its format can change dramatically in the near…
Nikita
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iCE40 IceStorm FPGA: Switchable Pullup on Bi-directional IO pins

How can I add a switchable pullup to a Tri-State pin? There are the "Tri-State" and the "Pull-Up" blocks in icestudio. I want to combine them into a "Tri-State with Pull-Up" block that has another input that allows to enable or disable the pull-up…
Ursin Solèr
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