How do I get multi-bit ports to work in Yosys when the module is BLIF?

Question

I cannot figure out how to get separate synthesis of modules to work in Yosys. Consider this simple two-module example:

bottom.v

module bottom(x, out);
    input  [0:7] x;
    output [0:7] out;
    assign out = x+1;
endmodule

top.v

module top(x, out);
   input  [0:7] x;
   output [0:7] out;
   bottom b(.x(x), .out(out));
endmodule

Now, synthesizing these together works as intended:

$ yosys -q -o top.blif -S top.v bottom.v
$

But if I first synthesize bottom.blif from bottom.v, I get an error message saying that there is no port out in the module bottom:

$ yosys -q -o bottom.blif -S bottom.v
$ yosys -q -o top.blif -S top.v bottom.blif
ERROR: Module `bottom' referenced in module `top' in cell `b' does not have a port named 'out'.
$

Why does this happen? Googling for issues, I have found references to the hierarchy command in contexts that I do not fully understand. I have tried running that command before synth, but it does not affect the result.

CliffordVienna · Accepted Answer · 2017-02-07T10:54:53.243

The BLIF file format does not support multi-bit ports. This has nothing to do with Yosys, it is simply a limitation of the file format. Thus, when writing a design with multi-bit ports to a BLIF file, all ports are automatically split into single bit ports. So in the BLIF file there is no 8-bit wide port out, there are 8 single-bit ports out[7], out[6], out[5], out[4], out[3], out[2], out[1], and out[0].

So when you try to mix the Verilog and BLIF files like you have described, the bottom module does not match the interface of the top.b cell anymore.

Edit: I've now added read_blif -wideports in git commit 7e0b776. This allows you to merge the individual single-bit ports again when reading a BLIF file back into Yosys. This way you can use BLIF as interchange format between Yosys and ABC without breaking module interfaces with multi-bit ports.

How do I get multi-bit ports to work in Yosys when the module is BLIF?

1 Answers1