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Questions tagged [yosys]

Yosys is an open-source framework for (Verilog) HDL synthesis and formal verification. It is highly customizable using scripts and a C++ extensions API.

Yosys is an open-source framework for (Verilog) HDL synthesis and formal verification. It is highly customizable using scripts and a C++ extensions API.

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Why this simple code causes extra slow PROC_DLATCH pass

I use (excellent) Yosys to synthetize (read_verilog & proc) the code below (gray incrementer logic for async fifo) to make some formal checks and found that it is incredibly slow. For W=2 it synthetizes in 0.2sec, W=3 in 230sec. It didn't end for…
Martin Devera
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Yosys / abc uses many gates instead of better monolithic cell

For a simple design and custom cell library, I am getting synthesis results in which Yosys / abc chooses a result that is obviously (for the human reader) worse, and which ignores an obvious alternative implementation. It seems to me that the result…
Martin Geisse
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Verilog and SystemVerilog supported

In the Yosys manual I read C.108 read -sv2005 -sv2009 -sv2012 load HDL designs Load the specified Verilog/SystemVerilog files. (Full SystemVerilog support is only available via Verific.) C.113 read_verilog – read modules from Verilog file -sv…
Øyvind Teig
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crash/problems with suprove solver

I have a fairly simple sequential problem I am trying to formally prove with a "mode prove" in symbiyosys I'm using "aiger suprove" as the engine and am getting the following crash: $ sby -f assert_seq_proof.sby SBY 9:02:40 [assert_seq_proof]…
turbo_fingers
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How to remove auto-generated YOSYS comments?

When I synthetize my verilog code using YOSYS the netlist generated contains comments like: (* src = "counter.v:6" *). I want to obtain a netlist file without these comments. This is my counter.v module counter (clk, rst, en, count); input clk,…
sudohumberto
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Synthesis verilog with Yosys

I want to synthesis a vhdl design for ASIC standard cell libraries to find the circuits area requirement. How can i do it for for Virtual Silicon (VST) standard cell library UMCL18G212T3 or UMC L180 0.18µm using Yosys? Does Yosys support vhdl code…
crypt
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How to reuse BRAM once it's not needed by module?

I'm working on a (seemingly) simple project as a learning exercise: connecting an SSD1331-based 96x64 PMOD display via iCEstick (Lattice iCE40HX-1k FPGA) to PC so I can send some RGB565-encoded image through USB to be shown on said display. Thing…
Viking
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Yosys: Variable initial value to flip-flop at reset

I am trying to assign an initial value to the FF at reset. The initial value is an input to the circuit. In the cell library I added the following FF: cell (DFF){ area : 0; ff(IQ,IQN){ next_state : "D"; clocked_on :…
Siam
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Yosys interpret and and not gate as nand for visualization

I was trying to use yosys purely for visualization in combination with https://github.com/nturley/netlistsvg. A tool which takes a yosys generated json file and creates an SVG out of it. If I have the verilog code: module test(a,b,c); input wire…
jackana3
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Increment integer under case state in verilog with yosys

I don't know if it's in Verilog-2005 standard but I managed to compile following code with «synplify pro» and «icarus verilog». integer fsm_step_number; always @(posedge clk or posedge rst) if(rst) begin pc <= 8'h00; wb_addr_o…
FabienM
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How to write std_logic_vector assignment with input-dependent range in VHDL?

I am trying to copy some part of a std_logic_vector into another, at a position (index) depending on an input. This can be synthesized in Vivado, but I want to use another tool (SymbiYosys, https://github.com/YosysHQ/SymbiYosys) for formal…
Robin Arbaud
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How to flatten Verilog bus to individual wires using Yosys

Simple question here. Is there a method in Yosys to flatten arrays? i.e.: wire [1:0] rdata; becomes wire rdata_1; wire rdata_0;
edc
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How to output dependency files in Yosys (gcc -MMD equivalent)?

Is there a command for Yosys, which creates a dependency file equivalent to the gcc option -MMD? (This option outputs a small Makefile fragment, which lists all files included by the compilation unit. See Using g++ with -MMD in makefile to…
Alexander
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ICE40 up5k Internal internal oscilator and ip's

i can see that icestorm support ice40 ultra plus up5k fpga, but this chip has internal osc, is there any example what i use it ? of course using yosys, icestorm (opensource) and is there some examples where i can use build in IP,s such as SPI,…
Miroslav Talasek
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Yosys instruction "sat -dump_cnf "

I have a sample combinatorial circult in Verilog where I can follow the instruction to do logic synthesis and generate blif file. However, what I need is to generate the CNF formula out of the circuit. Tools such as ABC only allows to generate from…
Chih-Hong
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