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Questions tagged [yosys]

Yosys is an open-source framework for (Verilog) HDL synthesis and formal verification. It is highly customizable using scripts and a C++ extensions API.

Yosys is an open-source framework for (Verilog) HDL synthesis and formal verification. It is highly customizable using scripts and a C++ extensions API.

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required size of a configuration file for a HX1K (in "SPI slave" mode)

I am reworking the programmer for the Olimex iCE40HX1K board (targetted towards a STM32F103 ma) where I also would like to implement the "SPI Slave" mode to configure an image directly into RAM without using the serial flash. Looking at the Lattice…
kristoff
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Superfluous buffers/inverters in synthesised netlist

This is another follow-up question to Combinatorial synthesis: Better technology mapping results. This is my Yosys TCL control script: yosys -import set libfile osu018_stdcells.lib read_liberty -lib $libfile read_verilog test.v hierarchy; procs;…
FriendFX
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yosys rtlil dumps incomplete

I'm trying to make sense of what yosys is doing to my verilog source, so I have inserted a number of dump processes into my script. I assume that these are in what the manual describes as ILANG? Looking through the dump immediately after reading in…
Bill Purvis
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Why is this MUX with const. inputs not optimised away?

This is a follow-up question to Combinatorial synthesis: Better technology mapping results. I am using Yosys (version 0.5+ (git sha1 f13e387, gcc 5.3.1-8ubuntu2 -O2 -fstack-protector-strong -fPIC -Os)) with the following synthesis…
FriendFX
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Some questions about wires with private name in Yosys

In one of the designs I compiled using Yosys I saw that we can have private wires (wires with private name). For example, $0_s0[127:0]. So, I have few questions about them: why do we have private wires in Yosys (what scenarios)? does it always get…
Mehrdad
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running ABC inside YOSYS returns ' Warning: Detected 1 multi-output gates'

When using YOSYS I call abc command: abc -liberty mycells3.lib mycells3.lib is a simple custom technology library based on the example library provided in YOSYS distribution where I added ADDER cell (named FAX1): library(demo) { cell(BUF)…
Omer Shlomovits
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How to put a list of cells into a submodule in yosys

I am trying to write a procedure to put each Strongly Connected Component of the given circuit into a distinct sub-module. So, I tried to add a function to SCC pass in Yosys to add each SCC into a submod. The function is: void…
Mehrdad
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How to create Gate Level Verilog from higher level Verilog using yosys

I am trying to generate Gate Level Verilog initially from a function described in C/C++ language. My C function is a simple and gate: _Bool and2gate(_Bool a, _Bool b) { return a && b; } Using Bambu-Panda tool http://panda.dei.polimi.it/ I…
AlexP
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Conditional compilation in ice40_synth using yosys?

I'm currently compiling a bitstream for my project in a Makefile. For the non-debug version of the build I use the following command: yosys -p "synth_ice40 -blif $@ -top system" $^ And for the debug version I use: yosys -p "verilog_defaults -add…
flatmush
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Yosys FSM Detection State Assignments?

I am attempting to use Yosys for a project of mine, but I am confused about the FSM detection. I read this post: FSM export using Yosys My question is about the state transitions detected from the Verilog file by Yosys. On the post that the link…
Abraham McIlvaine
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yosys fails at ABC pass (on counter.v demo)

I hope someone can help me with this... This is my first encounter with yosys. For the start, I'm trying to run the very same demo as Clifford explained in his presentation. I downloaded the demo at the following location:…
Boris L.
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What are the useful attributes that can be used with passes in Yosys?

What are the most useful attributes that can be used with passes in Yosys? Also, I was wondering if you could give me an example to set 'keep_hierarchy' for a specific module (namely "counter") using 'setattr'.
Mehrdad
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How to modify an AST from YOSYS? And how to synthesis a modified AST to Verilog code?

We know that we can get AST textfile of Verilog code. Now I want to modify the AST to get some new features, Is ANTLR right for this job,or which software should I use? Or How should I do? Then, I want to synthesis the modified AST to generate…
jason
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How to perform Depth First Search (DFS) inside a module starting from its ports?

I am trying to implement a new pass to calculate the sequential depth and complexity of a given module in Yosys. To do so, I am getting inspired by scc pass. To implement it, I need to specifically perform DFS starting from the module's input…
Mehrdad
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How to get the AST result as a textfile from YOSYS

We know that YOSYS (YOSYS for win32) can get an AST result using read_verilog _dump_ast command, but the result view in the command window. How can we get the result as a textfile from the command window? Thank you very much!
jason
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