Highest Voted 'yosys' Questions

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Why do I get "Module port is neither input nor output" for all wires?

The error I get when trying to run the program is: Yosys failed with code 1 unnamed.sv:5: ERROR: Module port `\D0' is neither input nor output. This happens for all the wires. module twobitmulti (A1, A0, B1,B0, P0, P1, P2, P3, C1, D0, D1, D2); …

verilog yosys

asked Apr 04 '22 at 15:29

Ghosty Toasty

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convert verilog to aiger with Yosys

I have several verilog files which I want to convert to aiger format using Yosys, I use the following commmad in yosys: read_verilog gclk_reg.v nld_and.v my_ff_W_8_.v gated_netlist.v synth_xilinx -flatten -top gclk_reg aigmap write_aiger -ascii…

verilog yosys

asked Jun 29 '21 at 02:51

张小禹

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iCE40 Ultra Plus 5k — how to set PLL (without propietary GUI tools) (continued)

In this question, I was suggested to use the existing libraries in order to test a PLL for the iCE40 Ultra Plus 5k. I bought the Icebreaker V1.0e board and it looks like this: External 12 MHz oscilator is connected to the pin 35 (marked green) of…

vhdl fpga yosys

asked Jun 24 '21 at 09:30

71GA

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Selecting the MFFC of a node

I need to determine the maximum fanout-free cone (MFFC) of nodes/cells in a circuit. As far as I am aware, there is no direct command in Yosys to do that. I thought it might be possible with the select command, but I have not figured out a correct…

yosys

asked Mar 24 '21 at 13:41

lwitsche

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YOSYS simulating a combinatorial circuit with a specific input

I have a very simple combinatorial circuit written in .blif, such as: .model circuit .inputs a b .outputs c .names a b c 11 1 .end Now I'd like to simulate it with yosys, and I'd like to specify the input. Basically, I am trying to replicate…

simulation circuit yosys

asked Jan 25 '21 at 15:49

Eelah

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how to estimation a chip size with standard cell library

I have recently started using yosys, synthesized a DSP block with cmos_cells.lib and got following results: ABC RESULTS: NAND cells: 2579 ABC RESULTS: NOR cells: 2771 ABC RESULTS: NOT…

yosys

asked Jan 01 '21 at 23:11

M.X

195
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System Verilog Loops

Im currently working on the Shift-Add Algorithm (32x32 bit Multiplication) in System Verilog. System Verilog cant find any error and my code is working correctly according to GTKwave. When I synthesize my circuit with yosys, Latches will be added.…

verilog system-verilog cpu-architecture hdl yosys

asked Nov 12 '20 at 19:22

d4mb

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Addition/Substraction Optimization in Yosys

I have the following very simple verilog module, which depending on the input op either performs a+b or a-b. module addsub (a, b, op, r); parameter DATA_WIDTH = 4; input [DATA_WIDTH-1:0] a, b; input op; output [DATA_WIDTH-1:0] r; …

synthesis yosys

asked Sep 03 '20 at 12:58

hu3

13
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How to preserve wires during Yosys ABC implementation step

I am implementing a simple circuit and want to preserve some wires during implementation using Yosys ABC. I am synthesizing using synth_ice40. I am using (* keep *) in my Verilog code to preserve the wires but I have noticed that after TECHMAP pass,…

synthesis yosys

asked Aug 17 '20 at 13:50

user3099006

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Yosys Error for long names (wires/instances)

I'm trying to run a large design with Yosys but I get the following error terminate called after throwing an instance of 'ord::Exception' what(): Net…

yosys

asked Aug 16 '20 at 23:35

ahmedafify

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how do I import sv packages using YOSYS

I was wondering how to import sv packages while using YOSYS. For instance In the file my_pkg.sv I have the following package my_pkg; parameter KL=64; endpackage Now in the file top.sv I have the following import my_pkg::*; module top( …

yosys

asked Jul 28 '20 at 15:24

guytout

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Understanding logic tile LC_5 bits

i m new to yosys and arachne-pnr. Here is the snippet from .asc and .icebox_explain. I could not understand how the bits of LC_5 are derived from .logic_tile 1 11. example.v module top (input a, b, output y); assign y = a &…

yosys ice40

asked Jul 13 '20 at 00:01

Sajjad

111
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Error "does map to unexpanded memory" in yosys verilog when using indexed part select

I'm having trouble understanding this error I'm getting in Yosys. I copied the relevant (I think) code below. reg signed [15:0] wb1 [0:131071]; reg signed [27:0] currentAttrWB [0:4094]; always @(posedge clk) currentAttrWB <= wb1[attrWBoffset +:…

verilog yosys

asked Jun 24 '20 at 10:43

ke10g

27
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1 answer

Drawing schematic out of yosys using Latex with CircuitTikZ and convert it into a PDF?

Drawing circuit diagrams using logic gates symbols like a traditional logic gate-level netlist. I saw the following: Drawing circuit diagrams (with logic gates) in…

yosys

asked Mar 09 '20 at 11:47

user7915059

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How to create a custom technology cell map for Yosys

I have the following simple Verilog design (in test.v): module digital ( input a, b, c, output reg q ); wire ena = a & b; always @ (ena, c) begin if (ena) q <= c; end endmodule Which models a simple latch with a gate on it's ena…

verilog yosys

asked Feb 10 '20 at 02:12

FriendFX

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Questions tagged [yosys]