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I'm having trouble understanding this error I'm getting in Yosys.

I copied the relevant (I think) code below.

reg signed [15:0] wb1 [0:131071]; 
reg  signed [27:0] currentAttrWB [0:4094];

always @(posedge clk)
currentAttrWB <= wb1[attrWBoffset +: 4094];

ERROR (on last line): "currentAttrWB does map to an unexpanded memory!"

What I'm trying to do is select a sub-range of 4095 16bit words in a long array of 131072 16bit words, using indexed part select (+:). This range would be offset within the long array using attrWBoffset. But obviously there is something I am not understanding. At first I thought this was because currentAttrWB was not large enough to contain 4095 16bit words. But I still get the error when bumping its register up to 28bits.

I guess I need to understand what is meant by expanded and unexpanded.

Thanks for your help.

ke10g
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1 Answers1

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Yosys does not support memories, i.e. anything defined as reg [x:0] mem[0:y]; being on the left hand side of an assignment. I am not sure if this is a Yosys limitation or a Verilog one, but such a pattern makes little sense for an FPGA application where memories are accessed one element at a time.

If Yosys could implement such a pattern, it would have to map the memory to LUTs and flipflops rather than use dedicated RAM resources, as such a simultaneous transfer isn't possible with block RAM. There are very few FPGAs with over 2 million flipflops available, and if you had one you probably wouldn't want to fill it up with something like this.

What you probably want is a counter that counts from 0 to 4094 and copies one entry every clock cycle until it completes.

gatecat
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    Thanks David. That's what I ended up doing. Thanks for clarifying why it wasn't working. – ke10g Jun 25 '20 at 15:34
  • Anyone else getting this error. I had it from a typo declaring the [n:m] on the right of the reg name (reg foo[1:0]). Moved to the left (reg [1:0] foo) and it fixed it. – douggard Jul 24 '20 at 17:03