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Drawing circuit diagrams using logic gates symbols like a traditional logic gate-level netlist.

I saw the following:

Drawing circuit diagrams (with logic gates) in LaTeX

https://tex.stackexchange.com/questions/32839/drawing-circuit-diagrams-with-logic-gates-in-latex

and was wondering if there is a plan [or if this idea is possible or not] to create a schematic out of the Verilog output into a PDF file using LaTex and CircuitTikZ?

I am still reading up on it. Are there plans to have a schematic GUI viewer in the long term for yosys? What would be the best way to get this at least looked at please?

A way to have a PDF view of logic gates symbols and D-type flip flops would really help.

user7915059
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1 Answers1

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Yosys has a schematic viewer via the "show" command. It doesn't handle complex designs very well, but it does allow you to "see" what's going on within a synthesized design.

To use it, read your design in and synthesize it. Then run the "show" command. Without an argument, it should show the whole design, although you can select just a portion of the design if you would like to show that.

Zip CPU
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  • `show`command previews a design as a flowchard more or less. Is there a way to display it more like an electronics schematics? – 71GA Jun 10 '21 at 14:58