1

I was wondering how to import sv packages while using YOSYS. For instance In the file my_pkg.sv I have the following

package my_pkg;
      parameter KL=64;
endpackage

Now in the file top.sv I have the following

import my_pkg::*;
module top(
    input logic i_clk,
    output logic o_done
);
endmodule

Yosys gives the following error:

top.sv:1: ERROR: syntax error, unexpected TOK_ID

I was expecting YOSYS to accept the syntax since I am merely importing the package into the top level file. This is a common way to import all the content of a package inside a module and hence avoid having to prefix the package name every time a package parameter is used inside the module. This works in Modelsim, VCS as well as in DC. Is there a way to accomplish this in Yosys?

guytout
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1 Answers1

2

Looks like Yosys (Yosys 0.9+1706 git sha1 ff4ca9dd, gcc 8.4.0-1ubuntu1~18.04 -fPIC -Os) does not support top level imports. One possible workaround is to use a tool to convert the SystemVerilog code into verilog and then feed the verilog code into Yosys. One such a tool is sv2v from Zach Snow (kudo to Zach for the hint) at https://github.com/zachjs/sv2v.

guytout
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