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I have several verilog files which I want to convert to aiger format using Yosys, I use the following commmad in yosys:

read_verilog gclk_reg.v nld_and.v my_ff_W_8_.v gated_netlist.v

synth_xilinx -flatten -top gclk_reg

aigmap

write_aiger -ascii my.aag

When I use the aigmap command, it show that cells like:

VCC LUT2 GND LDCE

cannot be replaced.

Unsurprisingly, the write_aiger command fails, showing that:

"ERROR: Unsupported cell type: VCC (VCC)".

So how can I map those cells to allowed cells of write_aiger?(I also used the abc -g AND command but it still failed)

Many Thanks!!

tomerpacific
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张小禹
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1 Answers1

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Use synth instead of synth_xilinx. This will map to a set of Yosys-internal gates that aigmap understands, rather than to a set of Xilinx primitives.

gatecat
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  • thanks a lot, I have tried synth command before, but it remaind that files like VCC.v LDCE.v .etc are missing, so how can I add such verilog library in the synth command? – 张小禹 Jun 30 '21 at 02:48
  • You can try `read_verilog +/xilinx/cells_sim.v` before `synth`. I'm not sure if your downstream tool will be happy with latches in a netlist, though – gatecat Jun 30 '21 at 09:34