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I have recently started using yosys, synthesized a DSP block with cmos_cells.lib and got following results:

    ABC RESULTS:              NAND cells:     2579
    ABC RESULTS:               NOR cells:     2771
    ABC RESULTS:               NOT cells:      447
    ABC RESULTS:        internal signals:     3728
    ABC RESULTS:           input signals:      133
    ABC RESULTS:          output signals:      128

I don't have access to commercial standard cell library at the moment, but I am trying to get an estimate of the die size for this design with, e.g., TSMC 28nm process.

I would appreciate if someone could help me with this

Thanks

toolic
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M.X
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1 Answers1

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There's no getting around needing a cell library for (roughly) the process you want. Once you have one, map to it and then run stat -liberty cells.lib to calculate total cell area.

gatecat
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  • trying to estimate the area, I used open source OSU standard cell libraries. I downloaded them from qflow project (opencircuitdesign.com). I particularly used gscl45nm.lib. and the result I got from `stat -liberty... ` for one of my modules was about 82000, however, I Was not sure about the unit. Is this number in nm2 or um2? – M.X Jan 03 '21 at 11:28
  • It will be in the same units as the cell library – gatecat Jan 03 '21 at 12:43