I am implementing a simple circuit and want to preserve some wires during implementation using Yosys ABC. I am synthesizing using synth_ice40. I am using (* keep *) in my Verilog code to preserve the wires but I have noticed that after TECHMAP pass, the wires are removed and I can not see them anymore when I View my text file using ice40_viewer.
Could someone please provide a solution or comment on why it is happening this way?
