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I'm trying to run a large design with Yosys but I get the following error

terminate called after throwing an instance of 'ord::Exception'
what():  Net logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.ccf has segments vector empty

I know I need to shorten the wire names but I was wondering if Yosys can automatically take care of that since it would take too long to do it manually

Christopher Moore
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ahmedafify
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  • I don't think Yosys has any limit to net name length that that net would be close to reaching. Nor does that sound like an error from Yosys. It is more likely an error in a downstream tool, but I am not sure if it is length related at all. – gatecat Aug 17 '20 at 09:34

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