Questions tagged [modelsim]

ModelSim is a popular simulator and debugging environment for VHDL, Verilog and SystemC. It is used in electronic design automation for development and verification of electronic (mainly digital) modules and systems for implementation on field-programmable gate arrays or integrated circuits.

ModelSim is a product by Mentor Graphics to simulate systems written in one of the hardware description languages (HDLs) VHDL or Verilog or the system-level modeling language SystemC.

Depending on the license, ModelSim offers all or a subset of the following features:

Source code editor
Compiler
Simulator
Waveform viewer
Interactive debugging such as breakpoints, stepping etc.
Signal tracing (dataflow) analysis
Code coverage analysis
Functional coverage analysis
Project file management

ModelSim integrates these features in a single configurable GUI, however, it can also be scripted via the Tcl language and controlled through command-line parameters which allows for automation of simulation and verification tasks.

756 questions

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1 answer

Modelsim VHDL testbench

This is my VHDL code in Modelsim. The problem is that output is uninitialized, as you can see in the image. Please tell me what's the problem with my code. library ieee; use ieee.std_logic_1164.All; use IEEE.NUMERIC_STD.ALL; entity circu_it is port…

vhdl modelsim

asked Sep 08 '20 at 09:44

barkaat azmat

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1 answer

The generate if condition must be a constant expression

I am trying to create an Immediate Generator for RISC-V assembly, but I have encountered an error with if statement. Here is my code in Verilog: module signextend(in, out, sel); parameter nin = 32; parameter nout = 32; input…

if-statement verilog modelsim

asked Aug 18 '20 at 07:29

Khoa Trần

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1 answer

Testbench clk not advancing

All my testbench is trying to do is verify whether or not the LED signal went high, but on Modelsim when I try and simulate it, the clock doesn't even start, but it initializes to zero. I can also step through my design so I don't appear to have an…

verilog simulation system-verilog modelsim

asked Jul 24 '20 at 16:04

tash7827

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0 answers

Failed to map the library when using ISE to simulate a program connected with Modelsim

ERROR: Failed to map the library Reason: couldn't execute "vmap": no such file or directory` I have tried to re-compile the Xilinx library, but failed. Could anyone spare time to give me some help?

hardware modelsim simulate xilinx-ise

asked Jul 23 '20 at 01:11

tranquil

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0 answers

initialize constant array of records from another constant in vhdl

I am writing constants for stimulus and having a problem with building constant form other constants. UPDATE: in the example below (provided by user1155120) library ieee; use ieee.std_logic_1164.all; package snippet_pkg is type pixel is record …

vhdl modelsim

asked Jun 17 '20 at 15:41

Ahmad Zaklouta

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1 answer

Modelsim/Questasim unit delay simulation

I would like to launch an unit delay RTL simulation using Questasim 10.1. I've looked how to compile the design and I see there is an option +delay_mode_unit for compiling verilog files. My design is vhdl. Is there an option for this kind of design?

vhdl modelsim questasim

asked Jun 09 '20 at 13:47

Mxm89

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0 answers

Modelsim ( Questasim 10.1) save results from a certain time and see schematic data

I ve launched a simulation for reproducing a bug. The bug happens after 1s of simulation time and so the simulation last too much. Is there a way to save only the waveform and the other infos from a certain point of the simulation (i.e. after 1s)?…

simulation modelsim questasim

asked Jun 09 '20 at 11:14

Mxm89

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2 answers

How to fix vector assignment (vlog-13069) error

My variable declarations are like below: output [6:0] dout_7seg_3, dout_7seg_2, dout_7seg_1, dout_7seg_0; wire [6:0] dout_7seg [3:0]; and I tried to assign each dout_7seg_i to dout_7seg [i] by coding like below: assign dout_7seg_3 = dout_7seg…

verilog system-verilog modelsim

asked Jun 07 '20 at 01:30

Ash

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1 answer

Verilog floating point arithmetic at compile time?

My Verilog testbench code defines a module with these parameters: parameter PHASE_BITS = 32; parameter real MAX_PHASE = 1 << PHASE_BITS; I cannot get MAX_PHASE to have the expected value 4294967296 or its approximation; ModelSim shows me 0 instead.…

verilog modelsim

asked Jun 06 '20 at 08:34

ris8_allo_zen0

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3 answers

How can I fix the error: can't mix packed and unpacked types?

I am trying to build a 4:1 multiplexer using 2:1 multiplexers that I've built. I am getting a few errors whenever I try typing the command vsim mux4_test. Array connection type 'reg$[1:0]' is incompatible with 'wire[1:0]' for port (sel): can't…

verilog system-verilog modelsim

asked Jun 01 '20 at 07:59

Yousef1111

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2 answers

VHDL component multiplexer don't return value in modelsim

I am trying to make an ALU with an adder, mux2 and mux4 component with port map. I have write the ALU it pass compiling OK. The problem is when I try in modelsim to give values, the adder works ok, but the mux2 (sub_module) & mux4 (sub_module x2)…

vhdl modelsim quartus mux

asked May 26 '20 at 17:02

BreeZeR

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1 answer

How to prevent ModelSIM from stopping during simulation?

I'm trying to simulate a down counter which I described using D-Latches in SystemVerilog but when I start simulating, ModelSIM stops working and I can not do anything. This is the down counter description `timescale 1ns/1ns module Down_Counter_Part5…

verilog system-verilog modelsim

asked May 14 '20 at 19:16

Mahdi

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0 answers

VHDL : a problem with integer to std_logic_vector conversion

In my code int_mm_add is defined as an integer and mm_add is defined as std_logic_vector(13 downto 0). I try to convert from integer to std_logic_vector using: mm_add <= std_logic_vector(to_unsigned(int_mm_add, mm_add'length)); int_mm_add is…

vhdl modelsim

asked May 14 '20 at 08:11

stasrez

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1 answer

Instantiating a Verilog Module inside of a VHDL architecture with Modelsim SE

I'm trying to compile a VHDL core that has a verilog core instantiated inside of it. Unfortunately, I'm not allowed to modify any of the code because they are in somebody else's library. The VHDL file was previously compiled inside of library…

vhdl verilog modelsim

asked May 12 '20 at 15:00

Pico99

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1 answer

How do I use flip flop output as input for reset signal

I have 3 D flip flops set up in a counter. Once it reaches 5 (101) I want to set the FF Reset inputs to high (with the OR gate). The Resets are active low. This almost works but, when I initially run the program, the Q outputs from the flip flops…

verilog modelsim circuit

asked May 10 '20 at 17:34

Pragash B

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