Modelsim VHDL testbench

Question

This is my VHDL code in Modelsim. The problem is that output is uninitialized, as you can see in the image. Please tell me what's the problem with my code.

library ieee;
use ieee.std_logic_1164.All;
use IEEE.NUMERIC_STD.ALL;
entity circu_it is 
port (A : in std_logic;
      B : in std_logic;
      C : in std_logic;
      D : in std_logic;
      Z : out std_logic );
end circu_it;
architecture Behavioral of circu_it
is
Signal E ,F ,M ,N , L: std_logic;
begin
M <= (A and B and C) after 5ns;
E <= (M or D) after 5ns;
N <= (B nor C) after 5ns;
F <= (N nand A) after 5ns;
L <= not F after 2ns;
Z <= L xor E  after 5ns;
end Behavioral;

The testbench of code is the following ......

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
entity delay_test is
end delay_test;
architecture stimulus of delay_test is
 component delay
 port (
      A : in std_logic;
      B : in std_logic;
      C : in std_logic;
      D : in std_logic;
      Z : out std_logic);
 end component;

 signal A: std_logic ;
 signal B: std_logic ;
 signal C: std_logic ;
 signal D: std_logic ;
 signal Z: std_logic ;
begin
 DUT: delay port map ( A => A, B => B, C => C, D => D, Z => Z);
 STIMULUS1: process
constant PERIOD: time := 100 ns;
 begin
 
 A <= '0';
 B <= '0';
 C <= '0';
 D <= '0';

wait for period;

 A <= '0';
 B <= '0';
 C <= '0';
 D <= '1';

wait for period;
 A <= '0';
 B <= '0';
 C <= '1';
 D <= '0';

wait for period;
 A <= '0';
 B <= '0';
 C <= '1';
 D <= '1';

wait for period;
 A <= '0';
 B <= '1';
 C <= '0';
 D <= '0';

 wait for period;
 A <= '0';
 B <= '1';
 C <= '0';
 D <= '1';

 wait for period;
 A <= '0';
 B <= '1';
 C <= '1';
 D <= '0';

wait for period;
 A <= '0';
 B <= '1';
 C <= '1';
 D <= '1';

wait for period;
A <= '1';
 B <= '0';
 C <= '0';
 D <= '0';

wait for period;
 A <= '1';
 B <= '0';
 C <= '0';
 D <= '1';

wait for period;
A <= '1';
 B <= '0';
 C <= '1';
 D <= '0';

wait for period;
A <= '1';
 B <= '0';
 C <= '1';
 D <= '1';

wait for period;
A <= '1';
 B <= '1';
 C <= '0';
 D <= '0';

wait for period;
A <= '1';
 B <= '1';
 C <= '0';
 D <= '1';

wait for period;
A <= '1';
 B <= '1';
 C <= '1';
 D <= '0';

wait for period;
A <= '1';
 B <= '1';
 C <= '1';
 D <= '1';
 wait;
 end process;
end stimulus;

This is caused by a typographical error. The virtual component name `delay `appears not to have a default binding, wherein you provided an entity with a compatible port interface list (`circu_it)` . As an architecture declarative item you can provide a configuration specification (`for DUT delay use work.circu_it;`) or rename `circu_it` to `delay,` or rename `delay` to `circu_it`. A configuration specification can also appear in a configuration declaration which is then simulated (note few synthesis tools support configuration declaration targets). — , Sep 08 '20 at 21:23

score 2 · Answer 1 · answered Sep 08 '20 at 10:14

2

Your design entity is circu_it. You have instantiated a component called delay. You either need to

write a configuration to bind the two together
change the name of either the component or the entity so that they are the same (so that default binding occurs).

answered Sep 08 '20 at 10:14

Matthew Taylor

13,365
3
17
44

There's also a component instantion with the reserved word `entity`, such as `DUT: entity work.circu_it port map (`... wherein the `circu_it` would have to have been previously analyzed (compiled) into the working library and the component declaration wouldn't be used or needed. – Sep 09 '20 at 01:50

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