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I am writing constants for stimulus and having a problem with building constant form other constants.

UPDATE: in the example below (provided by user1155120)

library ieee;
use ieee.std_logic_1164.all; 

package snippet_pkg is

type pixel is record
  x: std_logic_vector(3 downto 0);
  y: std_logic_vector(3 downto 0);     
end record;   

type array_pixel is array (natural range <>) of pixel;
constant array_1 : array_pixel(0 to 2) := 
  (0 => (x"0", x"0"),   
   1 => (x"1", x"1"),  
   2 => (x"2", x"2")  
  );
constant array_2 : array_pixel(0 to 3) := 
  (array_1'range => array_1,    
   3 => pixel'(x"3", x"3") 
);

constant element : pixel := (x => x"3", y => x"3");
constant array_3 : array_pixel(0 to 3) := array_1 & element;
constant array_4 : array_pixel(0 to 3) := array_1 & pixel'(x => x"3", y => x"3");

end package; 

library ieee; 
use ieee.std_logic_1164.all;

use work.snippet_pkg.all;

entity snippet_test is
end entity;

architecture foo of snippet_test is  
begin

PASSIVE: process  
begin  
  for i in 0 to 2 loop  
    report "array_1(" & integer'image(i) & ").x = " & to_string(array_1(i).x);
    report "array_1(" & integer'image(i) & ").y = " & to_string(array_1(i).y);
  end loop;
  for i in 0 to 3 loop  
    report "array_2(" & integer'image(i) & ").x = " & to_string(array_2(i).x);
    report "array_2(" & integer'image(i) & ").y = " & to_string(array_2(i).y);
 end loop;

wait;
end process; 
end architecture;

I have an array of records like below:

type pixel is record
  x  : std_logic_vector(3 downto 0);
  y  : std_logic_vector(3 downto 0); 
end record;

type array_pixel is array (natural range <>) of pixel;

and then I build a constant from this like this:

constant array_1 : array_pixel(0 to 2) :=
  (0 => (x"0" , x"0"),
   1 => (x"1" , x"1"),
   2 => (x"2" , x"2")
  );

Now I want to build another array with a bigger index using array_1 like this:

constant array_2 : array_pixel(0 to 3) :=
  (0 to 2 => array_1,
   3 => (x"3" , x"3")
  );

but I am getting this error in ModelSim:

fatal: (SIGSEGV) Bad pointer access. fatal: vsimk is exiting with code 211.

I am compiling via VUnit. Is this a bug in ModelSim or wrong VHDL coding?

UPDATE: ModelSim mentor graphic doesn't produce this error but it gives wrong values as below:

# ** Note: array_1(0).x = 0000
# ** Note: array_1(0).y = 0000
# ** Note: array_1(1).x = 0001
# ** Note: array_1(1).y = 0001
# ** Note: array_1(2).x = 0010
# ** Note: array_1(2).y = 0010

# ** Note: array_2(0).x = ?(16) U ?(66) ?(9)
# ** Note: array_2(0).y = ?(164) U ?(76) 1
# ** Note: array_2(1).x = ?(208) ?(81) ?(147) 0
# ** Note: array_2(1).y = ?(85) ?(88) U X
# ** Note: array_2(2).x = ?(238) ?(255) ?(238) ?(255)
# ** Note: array_2(2).y = 0UUU
# ** Note: array_2(3).x = 0011
# ** Note: array_2(3).y = 0011

only last index is right and the one which are assigned by 0 to 2 => array_1 are wrong.

Ahmad Zaklouta
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    Provide a [mcve]. Your third snippet requires 2008 wherein an aggregate can be constructed of elements of the array type as well as the type of array itself. Are you passing the -2008 flag to vcom? –  Jun 17 '20 at 16:27
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    It's possible to construct a [standalone test](https://i.stack.imgur.com/oUwJQ.jpg) that demonstrates your snippets are valid VHDL declarations when compiled with the vcom command line flag `-2008` (which can also be conveyed changing the value of `VHDL93` in your modelsim.ini file, see the Modelsim Users Manual). Support for -2008 aggregates may depend on the Modelsim release (which isn't reported here). –  Jun 17 '20 at 17:23
  • @user1155120 I tried the snippets you shared and ModelSim gave the same error. I guess as you said, maybe ModelSim Altera-Intel free edition doesn't support -2008 aggregates. – Ahmad Zaklouta Jun 18 '20 at 08:22
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    You can also comment out everything `array_2` just to prove that's the problem. You haven't provided a [mcve]. There's also a work around instead of `(0 to 2 => array_1,` use `(0 => array_1(0), 1 => array_1(1), 2 => array_1(2),` where all the elements are of the array type element type (matching pre-2008). There's never been a single VHDL implementation for -2008 that wasn't modified from an earlier revision, and there isn't a single fully compliant -2008 implementation.(12 years on). –  Jun 18 '20 at 08:46
  • @user1155120 I actually realized now that ModelSim mentor graphic student edition gives wrong values to array_2 as updated in the question description. which ModelSim release are you using? – Ahmad Zaklouta Jun 18 '20 at 12:18
  • I tried in EDA playground with Mentor Questa and it worked https://www.edaplayground.com/x/37qW – Ahmad Zaklouta Jun 18 '20 at 12:57

0 Answers0