Questions tagged [modelsim]

ModelSim is a popular simulator and debugging environment for VHDL, Verilog and SystemC. It is used in electronic design automation for development and verification of electronic (mainly digital) modules and systems for implementation on field-programmable gate arrays or integrated circuits.

ModelSim is a product by Mentor Graphics to simulate systems written in one of the hardware description languages (HDLs) VHDL or Verilog or the system-level modeling language SystemC.

Depending on the license, ModelSim offers all or a subset of the following features:

Source code editor
Compiler
Simulator
Waveform viewer
Interactive debugging such as breakpoints, stepping etc.
Signal tracing (dataflow) analysis
Code coverage analysis
Functional coverage analysis
Project file management

ModelSim integrates these features in a single configurable GUI, however, it can also be scripted via the Tcl language and controlled through command-line parameters which allows for automation of simulation and verification tasks.

756 questions

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1 answer

ModelSim unexpected z input

I'm building a simple 7-segment display. I didn't have errors when I was compiling the module and testbench. But, when I'm simulating, I keep getting z value as input. Why do I get the z? Verilog code as below : module dec_7seg(d, seg); input…

verilog modelsim

asked May 06 '20 at 00:38

Baum

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1 answer

Verilog waveform shows blue lines and Hiz for some variables

module half_adder(sum, carry, a, b); input a, b; output sum, carry; xor sum1(sum, a, b); and carry1(carry, a, b); endmodule module full_adder (fsum, fcarry_out, a, b, c); input a, b, c; output fsum, fcarry_out; wire half_sum_1,…

verilog modelsim

asked Apr 21 '20 at 16:59

Dawood Wasif

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2 answers

ModelSim simulation works but FPGA fails. What am I missing?

Sorry if anything in here seems obvious but I am starting out in this new FPGA thing and I really enjoy it so far but this is driving me crazy. Here is the Verilog code for a block that should in principle do the following to an 8 bit…

verilog fpga modelsim quartus intel-fpga

asked Apr 19 '20 at 05:30

Zacharie McCormick

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2 answers

In Modelsim/Questasim is there a way to increase the thickness of the wave lines?

Using Modelsim/Questasim 10.6b with a 4K monitor makes it difficult to see the lines for signals, especially std_logic signals, vectors are a little better. I was able to increase text size via edit->preferences but haven't found anything similar…

modelsim questasim

asked Apr 06 '20 at 18:38

Joe

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1 answer

modelsim command to choose a particular test in Verilog testbench

I have 4 test patterns and all written inside a case statement in the testbench. How to call each test at a time through command line during simulation?let me know the command line argument for choosing one testbench case at a time during…

case verilog command-line-arguments modelsim

asked Apr 04 '20 at 10:53

dineesh

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1 answer

Modelsim: Error: (vsim-3033)... Instantiation of 'MUT' failed. The design unit was not found

I'm getting the vsim-3033 error in ModelSim when I try including a sub module into a testbench for simulation. All code compiles fine (according to modelsims 'check marks'). The code here is obviously Verilog. I've seen the question "answered" a…

verilog modelsim

asked Mar 28 '20 at 22:39

Metric

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1 answer

Can't create projects (Modelsim)

I've been doing VHDL on ModelSim since the beginning of the semester and for some reason, I can't create projects anymore now. I even uninstalled and reinstalled Modelsim but I still can't make it work. Could I have some help?

vhdl modelsim

asked Nov 23 '19 at 18:56

snoopybroker

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2 answers

DPI-C and SystemVerilog External Compilation flow issue

ModelSim User's manual (v10.1c), in page 660, talks about the default autocompile flow (using vlog) and external compilation flow to get the the DPI-C to work in ModelSim. I'm able to get the auto-compile flow to work. I'm stuck with the external…

gcc system-verilog modelsim system-verilog-dpi

asked Nov 05 '19 at 19:42

ghertz

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1 answer

VHDL Implementing exclusive or data as a function

I'm trying to pack simple code into a function. Here is the VHDL code: process(CLK, RST) variable newdata : std_logic_vector(7 downto 0) := (others => '0'); variable tempdata : std_logic_vector(7 downto 0) := (others => '0'); begin if…

vhdl fpga xilinx modelsim

asked Nov 05 '19 at 12:44

Ezk13

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1 answer

First time in VHDL / MODELSIM : can't compile component [(vcom-1576) expecting END.]

I used to come here for C problems and/or Java. These days I'm learning VHDL and I'm currently stuck in a very small problem. I thought maybe some fresh eyes could give me the solution. I'm that close to get it. This is a simple 1-BIT ADDER [works…

compiler-errors vhdl fpga modelsim intel-fpga

asked Sep 18 '19 at 17:58

Sacha Ketchum

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3 answers

warning message at the prompt

I'm trying to simulate a testbench. I'm not getting the waveforms also i'm getting the following warning message at the prompt. Is it because of the=is warning that my code does not simulate? ** Warning: (vsim-WLF-5000) WLF file currently in use:…

warnings simulation wave modelsim

asked Apr 24 '11 at 21:22

kinirashmi

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3 answers

Output of D flip-flop not as expected

It is async reset. D flipflop when i change reset from one to zero, it doesn't immediately raise the output from zero to one. but when i add in @always ( posedge clk or posedge reset or negedge reset ) it immediately change Verilog: module…

verilog modelsim

asked Aug 28 '19 at 14:00

Mina Safwat

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1 answer

Incomplete assignment and latches

When incompletely assigning a value I get a latch. But why did I get a latch in the example below? I think there is no need for the latch of F output because it is defined at all values of SEL. Verilog code: always @ (ENB or D or A or B pr SEL) …

verilog modelsim

asked Aug 25 '19 at 22:54

Mina Safwat

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2 answers

How does this SIPO Works?

I am making an UART transceiver, and In that for Receiver section, I need a SIPO to convert the serial data into parallel one, A web search threw out a code which does the required function, I am not able to understand how this particular code…

vhdl modelsim

asked Aug 13 '19 at 07:42

FlyingDodo

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1 answer

vlog-7 error. failed to open design unit file in read mode

i am trying to run an example design by IntelFPGA, using a tcl script provided by Intel. It reports 'error (vlog-7) failed to open unit file "blabla" in read mode. No such file or directory (errno = ENOENT). i can not find the error. Then i tried a…

modelsim

asked Jun 25 '19 at 09:36

Pieter van Leeuwen

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