VHDL component multiplexer don't return value in modelsim

Question

I am trying to make an ALU with an adder, mux2 and mux4 component with port map. I have write the ALU it pass compiling OK. The problem is when I try in modelsim to give values, the adder works ok, but the mux2 (sub_module) & mux4 (sub_module x2) don't give output. I replace 2-3 times the mux code and the problem is the same. I only get UUUUUUUU values for outY. I have minimized the code.

ModelSim

Main ALU minimized

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity ALU7_minimal is
    Port ( inpA : IN STD_LOGIC_VECTOR (7 downto 0) :="10110001";
             inpB : IN STD_LOGIC_VECTOR (7 downto 0) :="00011001";
        ALUS0 : in  STD_LOGIC := '0';
            outY : out  STD_LOGIC_VECTOR (7 downto 0));
end ALU7_minimal;

architecture Behavioral  of ALU7_minimal is

component sub_module
port(x,y : in STD_LOGIC_VECTOR (7 downto 0);
s: in STD_LOGIC;
z: out STD_LOGIC_VECTOR (7 downto 0));
end component;


begin

U0: sub_module port map (inpA, inpB, ALUS0, outY );


end Behavioral ;

mux2-1

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity sub_module is
port(x,y : in STD_LOGIC_VECTOR (7 downto 0);
s: in STD_LOGIC;
z: out STD_LOGIC_VECTOR (7 downto 0));
end sub_module ;

architecture Behavioral of sub_module is

begin

process (x,y,s) is
begin
if (s ='0') then
z <= x;
else
z <= y;
end if;
end process;

end Behavioral;

Provide a [mcve]. [The problem can't be replicated](https://i.stack.imgur.com/qBbt5.jpg) from the information provided using inputs gleaned from the linked waveform. Note U3 (adder8bit) is unbound (and isn't responsible for all the 'U's),`out0` is driven but not used as an input, nor is `out12`. — , May 26 '20 at 21:33
Now if you'd only provided a reproducible example. [The problem still can't be replicated](https://i.stack.imgur.com/DQrKI.jpg) from the information using inputs gleaned from the linked waveform. Consider providing (and using) a testbench. You appear to be doing something procedurally wrong. — , May 26 '20 at 23:28
Thanks again. That is exactly the problem. The code is simple but still producing error. Maybe the problem isn't in the code and there is a setting in Modelsim that need to look at? Do you know any other test environment that I can try the same code? — BreeZeR, May 27 '20 at 10:09

score 0 · Answer 1 · answered Jun 07 '20 at 06:50

0

no need for a process!

begin
with s select
    z <= x  when '0',
         y  when '1',
        'U' when others;

answered Jun 07 '20 at 06:50

Hamid R. Tanhaei

126
4

1

Please add some explanation to your answer such that others can learn from it – Nico Haase Jun 07 '20 at 11:05
A concurrent assignment statement is elaborated into a process with an equivalent sequential assignment statement. – Jun 12 '20 at 18:54

score 0 · Accepted Answer · answered Jun 12 '20 at 17:05

Just for future reference for others that experience the same problem (My teacher discover it): You needed to import into the modelsim all components files before you run the simulation. Paradox the adder of 1bit and 8bit was working even if I haven't import them, but the mux(2-1 /4-1) won't given any result. When I imported all the component files (and not just the main program), the ModelSim show the results correctly. Thank for your time and help guys, really appreciate.

And again the problem can't be replicated from the question. How does that aid future readers? — , Jun 12 '20 at 18:56

VHDL component multiplexer don't return value in modelsim

2 Answers2