Questions tagged [modelsim]

ModelSim is a popular simulator and debugging environment for VHDL, Verilog and SystemC. It is used in electronic design automation for development and verification of electronic (mainly digital) modules and systems for implementation on field-programmable gate arrays or integrated circuits.

ModelSim is a product by Mentor Graphics to simulate systems written in one of the hardware description languages (HDLs) VHDL or Verilog or the system-level modeling language SystemC.

Depending on the license, ModelSim offers all or a subset of the following features:

Source code editor
Compiler
Simulator
Waveform viewer
Interactive debugging such as breakpoints, stepping etc.
Signal tracing (dataflow) analysis
Code coverage analysis
Functional coverage analysis
Project file management

ModelSim integrates these features in a single configurable GUI, however, it can also be scripted via the Tcl language and controlled through command-line parameters which allows for automation of simulation and verification tasks.

756 questions

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2 answers

Concatenation of two arrays with specific range in one array in SystemVerilog

I was trying to store two specific spans of an array inside another array, but I get an error. What I want to do: I have [8-1:0]A as module input, and I wanna store : logic [8-1:0]temp = {A[4:7],A[0:3]}; but, when I simulate my module in test bench,…

asked Apr 14 '21 at 12:35

ryhn

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0 answers

# ** Fatal: (vsim-3807) Types do not match between component and entity for port

I have some problems with my VHDL file: I want to multiply 14-Bit values. For this I just used the template provided in Quartus prime and modified it slightly. Compiling my Code works fine, but if I try to simulate it with a .vwf file I always get…

vhdl modelsim

asked Mar 30 '21 at 10:15

sellerBasti

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0 answers

Why do I get this as an empty opt-design?

library IEEE; use IEEE.std_logic_1164.all; entity seg7ctrl is port ( mclk : in std_logic; reset : in std_logic; d0 : in std_logic_vector(3 downto 0); d1 : in std_logic_vector(3 downto 0); abcdefg : out std_logic_vector(6 downto 0); c : out…

vhdl implementation modelsim vivado

asked Mar 26 '21 at 15:48

pkrist

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1 answer

To Add if else statement into While loop VHDL

I am trying to work on inserting if else to loop but it is still expecting some syntax. I cant figure out why this if/else statement wont compile. I am new to VHDL, please help. This is one of the steps along the way and i am stuck. variable i :…

vhdl modelsim

asked Mar 10 '21 at 09:15

JOHNPAUL LANZADERAS

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0 answers

VHDL: Cache memory output signal not consistent and varies between either halfs of the output being right, but never the whole thing

I hope you guys are well :) I am trying to implement a simple cache memory system, however I am finding myself unable to properly do so. When I attempt to test my read miss/ read hit, I am getting the following result: VHDL Signals. As I understand…

caching memory vhdl modelsim

asked Feb 25 '21 at 18:29

TheHomelessRedRanger

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1 answer

Illegal assignment: Cannot assign an unpacked type to a packed type

In SystemVerilog I wrote: module mult32x32_arith ( input logic clk, // Clock input logic reset, // Reset output logic [63:0] product // Miltiplication product ); logic left_decoder, right_decoder,…

verilog system-verilog modelsim

asked Dec 28 '20 at 12:40

user14891163

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2 answers

ModelSim 10.5 All Optimizations are Disabled Error

I am running ModelSim SE-64 10.5 on windows 10 and when I wanna simulate any module I run into the following error: vsim -gui work.registerFileTB -novopt # vsim -gui work.registerFileTB -novopt # Start time: 15:20:14 on Dec 23,2020 # ** Error…

verilog modelsim

asked Dec 23 '20 at 12:22

aboloo

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1 answer

Why does ModelSim simulation freeze?

This is the Verilog code for '10101' non overlapping sequence detector. When I compile this code, it doesn't show any error. But, when I simulate the code, ModelSim stops working and freezes indefinitely. I cant find the error or where the problem…

verilog modelsim

asked Dec 14 '20 at 20:10

shubham737

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0 answers

Spikes or glitches in Modelsim

I've been learning VHDL for a while and I'm making a project right now. I made a NCO (Numerically controlled Oscillator) and a cordic algorithm to produce sine and cosine with a certain frequency. I don't know why I get spikes on my waves in…

vhdl simulation modelsim waveform

asked Dec 11 '20 at 10:30

Luigi Lombardi

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1 answer

Two to one mux in Verilog giving errors for unable to bind for a case statement?

compiler errors: lastname_dp.v:17: error: Unable to bind parameter sel' in testbench.dpTWOTOONEMUX' lastname_dp.v:17: error: Cannot evaluate genvar case expression: sel code: module twotoonemux(input wire [31:0] input1, input wire [31:0] input2,…

verilog modelsim

asked Nov 22 '20 at 23:16

William

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1 answer

VHDL "expecting type ieee.std_logic_1164.STD_LOGIC_VECTOR" when that is the type I'm giving

library IEEE; use work.vec9Arr.all; use IEEE.STD_LOGIC_1164.all; entity vector_scalar_multiplier is port( in_a : in vec9arr; in_b : in std_logic_vector(15 downto 0); out_vec : out vec9arr); end vector_scalar_multiplier; architecture…

vhdl modelsim

asked Nov 21 '20 at 05:07

Noah Thompson

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1 answer

Strange behavior when running a piece of verilog code on modelsim

I have a problem when running this piece of Verilog code in ModelSim. I have built a circuit that is supposed to count the milliseconds. The circuit(module numarator) consists of two blocks: a circuit which receives a 5MHz frequency clock…

verilog counter modelsim digital preset

asked Nov 20 '20 at 09:50

pauk

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1 answer

ALU test bench using test vector file not working

I'm new to this, and the question might seem silly, but I've spent hours on this and the test bench just doesn't want to load the right values into the register before performing the arithmetic. Here's what happens when I go to run the simulation #…

verilog hdl modelsim test-bench alu

asked Oct 23 '20 at 02:17

Pete

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1 answer

I am getting unknown value when doing a 4 bit shifter verilog (gate level)

I am trying to implement a 4 bit right shifter using gate level but i got unknown result for some reason, my mux work ok but when i try testbench for my shifter it give back something like this: a=0010 b=01 c=0000 a=1111 b=01 c=00xx Please help!!!!…

verilog system-verilog fpga modelsim

asked Oct 10 '20 at 05:38

Dang Nhat

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1 answer

Verilog self checking testbench will not run? Building a simple ALU, this shouldn't be so hard

I am tasked with building an ALU. However, I must not understand how the testbench should run. I have run other simple testbenches just fine. code compiles (using quartus) made a text file and turned it into a "test.tv" file opened modelsim and…

verilog system-verilog hdl modelsim quartus

asked Sep 11 '20 at 19:55

Preston

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