How to prevent ModelSIM from stopping during simulation?

Question

I'm trying to simulate a down counter which I described using D-Latches in SystemVerilog but when I start simulating, ModelSIM stops working and I can not do anything.

This is the down counter description

`timescale 1ns/1ns
module Down_Counter_Part5 (input RST,CLK,EnableIN, output[7:0] Qout, output EnableOUT);

    genvar i;
    wire[8:0] En;
    wire[7:0] D,Qbar;

    assign En[0] = EnableIN;
    assign EnableOUT = En[8];

    generate
        for (i=0; i<8; i=i+1) begin
            assign D[i] = (Qout[i] ^ En[i]) & (~RST);
            assign En[i+1] = Qbar[i] & En[i];
            Clocked_D_Latch Ii (D[i],CLK,Qout[i],Qbar[i]);
        end
    endgenerate

endmodule

And It's my testbench

`timescale 1ns/1ns
module Testbench_Part6 ();

    logic rst = 1,clk = 1,enablein = 1;
    wire[7:0] qout;
    wire enableout;

    Down_Counter_Part5 UUT (rst,clk,enablein,qout,enableout);

    initial repeat (5) #5000 rst = ~rst;

endmodule

How can I solve the problem?

Isn't it the clk signal you want to toggle? – Moberg May 14 '20 at 20:54 — Moberg, May 14 '20 at 20:54
it stops at 0ns and nothing happens then – Mahdi May 14 '20 at 21:54 — Mahdi, May 14 '20 at 21:54
Yes I want to toggle clk but none of them work properly – Mahdi May 14 '20 at 21:55 — Mahdi, May 14 '20 at 21:55

score 0 · Accepted Answer · answered May 15 '20 at 16:49

You have a zero-time infinite combinational feedback loop. This will cans the simulator to timeout or appear to hag.

I'm assuming the latch is transparent when CLK is high; you didn't show that bit of code. Therefore Qout will equal D when CLK is high. But when En is high, then D will be equal the the invert of Qout. Since there is not time blocking, Qout will be reevaluated, causing another update to D, causing another update to Qout, and on and on forever.

If you are only going to simulate this, then add a little delay to the assignment so you can see the feedback loop in wavefrom/logfile. I would also suggest starting RST as 0 so the X and Z values can be flushed out.

assign #1 D[i] = (Qout[i] ^ En[i]) & (~RST);

Adding the #1 is not a proper solution for real design. A proper solution requires the all signals to be in a determinable at each time step without # delays.

How to prevent ModelSIM from stopping during simulation?

1 Answers1