I would like to launch an unit delay RTL simulation using Questasim 10.1. I've looked how to compile the design and I see there is an option +delay_mode_unit for compiling verilog files. My design is vhdl.
Is there an option for this kind of design?
By refering to Modelsim 10.1c User Manual- Chapter 7, Cell Libraries, you can find how Modelsim can support various Verilog ASIC and FPGA cell libraries. Unit Delay Mode is explained one page after in the manual.
Concerning VHDL, I can't find a similar section where Modelsim has a confirmed support. However, in Chapter 14, VHDL VITAL SDF, you can find how to enable timing for VITAL cells only. You can read the following section SDF to VHDL Generic Matching for more help.
Also have a look at Chapter 6, VITAL Usage and Compliance on how to make a working setup for VHDL.
