Instantiating a Verilog Module inside of a VHDL architecture with Modelsim SE

Question

I'm trying to compile a VHDL core that has a verilog core instantiated inside of it. Unfortunately, I'm not allowed to modify any of the code because they are in somebody else's library.

The VHDL file was previously compiled inside of library "wildcores", and the verilog file was compiled inside of library "work".

The problem occurs because Modelsim doesn't know to automatically search the work library when compiling a VHDL source file in a different library. (See Error below.)

Is there a way to fix this problem by adding flags to the modelsim SE compile command without modifying any of the code?

FILE: core2.v

`timescale 1ns/10ps

module core2(
    input  wire A,
    output wire Z
);

   assign Z = A;

endmodule

FILE: core1.vhd

Library IEEE;
use IEEE.std_logic_1164.all;

library wildcores;

entity core1 is 
   port(
       A : in  std_logic;
       Z : out std_logic
   );
end entity;

architecture rtl of core1 is
begin
   core2_inst: core2 
        port map(
            A => A,
            Z => Z
        );

end architecture;

FILE: run.sh

#!/bin/bash
# Modelsim SE Compile Script:

set -o verbose

vlib wildcores

vlog -work work core2.v || exit 1

vcom -work vhdlcores core1.vhd || exit 1

vopt core1 -o sim || exit 1

vsim sim

output:

$ ./run.sh

vlib wildcores
** Warning: (vlib-34) Library already exists at "wildcores".

vlog -work work core2.v
Model Technology ModelSim SE-64 vlog 10.7a Compiler 2018.03 Mar 27 2018
Start time: 10:49:17 on May 12,2020
vlog -work work core2.v
-- Compiling module core2

Top level modules:
        core2
End time: 10:49:18 on May 12,2020, Elapsed time: 0:00:01
Errors: 0, Warnings: 0

vcom -work vhdlcores core1.vhd || exit 1
Model Technology ModelSim SE-64 vcom 10.7a Compiler 2018.03 Mar 27 2018
Start time: 10:49:18 on May 12,2020
vcom -work vhdlcores core1.vhd
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity core1
-- Compiling architecture rtl of core1
** Error (suppressible): core1.vhd(16): (vcom-1141) Identifier "core2" does not identify a component declaration.
** Note: core1.vhd(22): VHDL Compiler exiting
End time: 10:49:18 on May 12,2020, Elapsed time: 0:00:00
Errors: 1, Warnings: 0

Verilog has no knowledge of libraries. Also, work is not a library in itself - it is the working library. And finally - VHDL has no visibility of verilog. Hence you need to write a component for your Verilog in VHDL: and let the elaboration map the component to the Verilog Module. — Tricky, May 12 '20 at 15:11
I compiled the Verilog into the same library as VHDL and that seemed to work... — Pico99, May 12 '20 at 18:27

score 0 · Answer 1 · answered May 12 '20 at 20:49

0

#!/bin/bash
# Modelsim SE Compile Script:

set -o verbose

vlib work
vlib wildcores

# I think, this is the line that fixes it..
vmap wildcores work

vlog -work work core2.v || exit 1

vcom -work vhdlcores core1.vhd || exit 1

vopt core1 -o sim || exit 1

vsim -c -t '1fs' sim

answered May 12 '20 at 20:49

Pico99

31
1
5

is this an answer or an addition to your original question? – Tarick Welling May 13 '20 at 10:58
its the answer.... the purpose of the modelsim "vmap" command is to add an alternative library (second argument of vmap) to search if the unit is not found in the primary library (first argument of vmap). So basically you need to put your verilog in a different library and then tell your vhdl library to logically join itself to the verilog library... it first searches the vhdl library, then it searches the verilog library that was logically linked to it with vmap. you could for instance compile your verilog into library "vlog -work vercores"... then "vmap vhdlcores vercores".. – Pico99 May 14 '20 at 21:15

Instantiating a Verilog Module inside of a VHDL architecture with Modelsim SE

1 Answers1