Questions tagged [iverilog]

`iverilog` is a compiler that translates Verilog source code into executable programs for simulation, or other netlist formats for further processing.

iverilog is a compiler that translates Verilog source code into executable programs for simulation, or other netlist formats for further processing. The currently supported targets are vvp for simulation, and fpga for synthesis. Other target types are added as code generators are implemented.

Official site: http://iverilog.icarus.com
Source code: https://github.com/steveicarus/iverilog
Wikipedia

176 questions

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1 answer

How to add all, except one file in iverilog command line instruction from a folder?

I understand that if I want to include all the Verilog files I can do so by adding files like this: iverilog /Users/kp/Desktop/all_new2/*.v -s testbench.v which takes all files in all_new2 folder and sets testbench.v as the top module. However, I…

asked Jun 30 '20 at 05:49

Kiran

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1 answer

Passing a single row of a 2d array as an input to a module in verilog

I was wondering if there is any way to pass a single row of a 2d array of values as the input to a module in Verilog. Say my array is defined like this: reg[15:0] arr[0:9][0:63]; ... ... mod1 m(..., arr[5], ....); mod1 has the…

arrays verilog system-verilog iverilog icarus

asked Jun 01 '20 at 14:30

Akilesh Kannan

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1 answer

My statements come out as XXXXXX instead of the default value in a case statement. in verilog HDL

Edit:I forgot to add a i =i+1, the code works but it still doesn't work for the 0 value which is what I am trying to fix now. I am trying to simulate a 3 digit 7segment led array so I'm taking in a constant input(in this case 1,2,3...) which is in…

verilog fpga hdl iverilog

asked May 29 '20 at 07:26

Sam

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1 answer

MUX in iVerilog: Unable to bind parameter/cannot evaluate genvar expression errors

Will someone please take a look at my code and explain why I am getting these errors. I am brand new to iverilog. This is for a project Power_ALU.v:13 error: Unable to bind parameter 'select' in 'Power_ALU_tb.ALU8' Power_ALU.v:13 error: Cannot…

verilog mux iverilog

asked May 11 '20 at 22:19

Stephen Greer

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1 answer

Why the vivado 2017.4 is showing error here?

My code is: module circuilar_fifo; localparam B=3,W=2; input wire clk,reset,wr,rd; input wire [B-1:0] wr_data; output wire [B-1:0] rd_data; output wire full,empty; Isn't this one of the correct method of declaring input outputs? But why does the…

verilog xilinx vivado vlsi iverilog

asked May 04 '20 at 11:49

Prasanna Shanbhogue

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1 answer

icarus verilog specify delays not respected if there are conditionals

Trying to model a 74245 with delays representative of the HCT device. I am finding that the timings I'm providing in a specify block are not respected. I have added an extra route A->C (not part of my orig design) to illustrate that the delays can…

delay system-verilog iverilog icarus

asked Mar 30 '20 at 20:09

John Lonergan

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1 answer

simple adder + testbench returning "dont care" input

i have a simple test bench for an adder module, but I am getting the wrong input: module adderTestbench; wire [31:0] fromAdd; adder lol(32'h00000000,fromAdd); initial begin //forcing program to be sequential #100; //wait 100 …

verilog iverilog

asked Mar 08 '20 at 05:30

Nak Leng

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3 answers

How can I assign module arguments in Verilog?

I have a verilog module that has a very long list of inputs and outputs that are required. module…

verilog hdl iverilog

asked Feb 10 '20 at 04:22

ched

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1 answer

Syntax error in code for JK Flip Flop using primitive

primitive ffjk (Q, Clk, set, reset, J, K); output Q; input Clk, set, reset, J, K; reg Q; table // Clk set reset J K : Q : Qnew ? 1 0 ? ? : ? : 1; ? 0 1 ? ? : ? : …

verilog hdl iverilog

asked Dec 22 '19 at 16:10

Jatin Sharma

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1 answer

Parameterize parameters?

I would like to parameterize localparam parameters. My module definition: module native #( parameter SIM_ONLY = 0, parameter FREQ = 500 )( ... ); I have lots of instantiations using the same localparam parameter A. if (FREQ == 550) begin …

system-verilog iverilog

asked Nov 26 '19 at 00:15

Alexis

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47

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1 answer

Verilog, can't generate bitstream

First timer in Vivado Verilog here, I just finished my coding for a project and simulation for the project. I keep getting error message when trying to generate bitstream... I think my syntax is correct, just can't figure out what's wrong. This is…

verilog vivado iverilog

asked Nov 20 '19 at 07:14

Javanewbie

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1 answer

Understanding the Verilog Stratified Event Queue

I'm trying to understand how the Verilog scheduling algorithm works. The below example outputs 0, xxxx and not 1010. I'm not clear why. If I do put a delay before $display, it would output 1010. module test; reg [3:0] t_var; initial begin …

verilog system-verilog iverilog

asked Oct 19 '19 at 20:33

cmutex

1,478
11
24

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1 answer

Syntax checking with iverilog

I want to run iverilog just to check syntax in my file. I don't want it to actually compile anything since I'm working on a large codebase and don't want to find and "include" all included files. `include "header.vh" // not a file in current dir…

verilog iverilog

asked Aug 18 '19 at 00:36

Sumanth Sridhar

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2 answers

What exactly is "Current Simulation Time" and Event Queue in Verilog?

Consider the below example: module test; reg a; initial begin a = 1'b0; a <= 1'b1; $display(a); end endmodule The above example displays 0. My reason is because the non-blocking assignment will be assigned at step 3 of the "Stratified…

verilog system-verilog system-verilog-assertions iverilog

asked Jun 09 '19 at 20:24

cmutex

1,478
11
24

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2 answers

Instantaneous module does not perform subtraction properly

I am trying to perform subtraction when ALX is 1 and ALY is 0 using instantaneous carry look ahead adder but it does not work properly. It works fine for addition. if ALX is 0 and ALY is also 0 it will load input to output if ALX is 0 and ALY is …

verilog iverilog

asked Apr 21 '19 at 18:22

Lau Chok Yip

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