Syntax error in code for JK Flip Flop using primitive

Question

  primitive ffjk (Q, Clk, set, reset, J, K);
    output Q;
    input Clk, set, reset, J, K;
    reg Q;
    table
//      Clk  set  reset  J   K   :  Q  :  Qnew
        ?     1     0    ?   ?   :  ?  :    1;
        ?     0     1    ?   ?   :  ?  :    0;
        ?    10     0    ?   ?   :  ?  :    -;
        ?     0    10    ?   ?   :  ?  :    -;
       01     0     0    0   0   :  ?  :    -;
       01     0     0    0   1   :  ?  :    0;
       01     0     0    1   0   :  ?  :    1;
       01     0     0    1   1   :  0  :    1;
       01     0     0    1   1   :  1  :    0;
        ?     0     0    ??  ??  :  ?  :    -;
    endtable
endprimitive

module ff(Q, Clk, set, reset, J, K);
    input Clk, set, reset, J, K;
    output reg Q;
    
    ffjk M1(Q,Clk,set,reset,J,K);
endmodule

I made a primitive of JK FF. Then I made a module and used the primitive inside it. I have also written a testbench to execute this code. I am constantly getting syntax error in the 2nd line.

jkff.v:2: syntax error

Answer 1

This is a problem with iverilog. It's only accepting very old Verilog syntax. Write the reg declaration on a separate line.

primitive ffjk (Q, Clk, set, reset, J, K);
    output Q;
    input Clk, set, reset, J, K;
    reg Q;

The correct way to write this in Verilog-2001/SystemVerilog is

primitive ffjk (output reg Q,
                input Clk, set, reset, J, K );

Then you will run into problems with the table. You'll have to ask another question if you can't figure that out.