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i have a simple test bench for an adder module, but I am getting the wrong input:

module adderTestbench;

    wire [31:0] fromAdd;

    adder lol(32'h00000000,fromAdd);


    initial begin //forcing program to be sequential
    #100; //wait 100
    end //end begin

    initial begin
    $display("%h",fromAdd);
    end

endmodule

module adder(addIn,addOut);
input [31:0] addIn;
output reg [0:31] addOut;
always @(addIn) 
begin
addOut <= addIn + 32'h00000004;
end
endmodule

It displays xxxxxxxx.

Can anyone explain why it is not displaying 4, instead it's displaying x's?

toolic
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Nak Leng
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1 Answers1

2

The code marked as "//forcing program to be sequential" does not make any code sequential.
Your two initial statements will still run in parallel. You probably mean:

initial
begin
   #100; //wait 100
   $display("%h",fromAdd);
end
Oldfart
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  • this helped for sure, but just let me know if I'm understanding correctly: what makes your code sequential is the fact that the #100 is inside the inital statement. Since the code in my OP has #100 outside of it, verilog will just run both the code with #100 and the display at the same time, essentially doing nothing that I want? – Nak Leng Mar 08 '20 at 11:15
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    Yes, exactly. Knowing that you need a delay is what 99% of the Verilog beginners have a problem with. So you outperformed those! Just the way the delay was set was wrong. All initial statements are executed simultaneous in parallel. – Oldfart Mar 08 '20 at 12:04