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Questions tagged [iverilog]

`iverilog` is a compiler that translates Verilog source code into executable programs for simulation, or other netlist formats for further processing.

iverilog is a compiler that translates Verilog source code into executable programs for simulation, or other netlist formats for further processing. The currently supported targets are vvp for simulation, and fpga for synthesis. Other target types are added as code generators are implemented.

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How to display values of "parameters" and "localparaters" in gtkwave iverilog simulation?

Gtkwave is displaying all the registers and signal values in the simulation using iverilog, but I can not find a way to display the parameters and localparameter values. Any advice?
AZ123
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Sync RAM related

I am trying to simulate the following code for an synchronous ram in Verilog. When I am trying to write in a specific address, dataOut is not coming the way I was expecting. It is skipping 1 address while reading data in the specified address. Can…
Sobebar Ali
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Assign value to only one bit in a vector module output

I have the following code and I get an error. I am trying to use only one bit out of the four lines in the inputs A, B, and the output, Y. To be clear, I do not want to use the AND operator, I want to use the AND module that I…
Mr_Doggus
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Verilog Error: "Syntax in assignment statement l-value." when writing a simple alu

I am having trouble finding the syntax error in this code of a simple simulator of MIPS alu functions. The error appears in the else of the case 6'b001000: // addi: ALU_.v:112: syntax error ALU_.v:113: Syntax in assignment statement l-value. And…
wastecvd
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Why are the bits in this Verilog wire assigned as 'z'?

I am trying to create a multiplication module in Verilog for an ALU project. When I pass test values to this modules, 0100101010011100 and 0100110000000000 and print these values with $display(), they appear normal. However, if I try to print one…
Kirill Polovtsev
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Implement a state machine in Verilog using a 2D array as transition table

I'm trying to implement a very simple Mealy state machine in Verilog. I have already done it with case and if statements, but I want to be able to do the same using a 2D array as transition table, for clarity. Here is the code: module ex10_1_2( //…
Dan
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Verilog syntax error whenever I run the vvp command

I'm encountering an error with running my testbench as whenever I input try to run it with the vvp command, I only get a message that reads "SantiJ1.v:1:syntax error". I've looked through my code and there doesn't seem to be a problem, at least from…
Ram Santiago
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Sequence of 3 or more ones: Verilog debugging

I'm new to Verilog coding and stuck with an error in my code. Can someone help to debug it? Main code: module tff (q,t,clk,clear); input t,clk,clear; output reg q; always @(negedge clk or posedge clear) begin if (clear) q <= 0; else…
Anonymous
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verilog alu design why all my output result is always 00000000

Here is my code, the professor say module format cannot be changed. And the homework also require only the input can be load when rst_n=1, and the output should be 0 when rst_n = 0. But in test bench all my result always is 00000000, zero is 1, cout…
sdragon
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Issue with an 8-bit ALU: the program won't stop and I need to verify that the specifications are reached

I have a big issue with an 8-bit ALU. To begin with, the code won't stop running. Second, a chart of specifications was given, and I believe I'm missing some of them Here are the specifications: Specification Data Inputs: A (8-bit), B…
GHG HGH
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Syntax in assignment statement l-value

This is code and can't recognize the error it's showing new_content as error. I changed its name, but error are also showing I thing this is a logical error module IF_ID(new_content, instruction, newPC, clk, pwrite1); input pwrite1, clk; input…
Panda
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Rotations Operations for 16bit ALU using multiplexers (updated question)

I'm new to this topic, with less knowledge about the coding part of it. But is there a way to implement multiple bit rotate operations using multiplexers for 16bit ALU ? I know the understanding, but not the coding part in iVerilog. I did barrel…
aLIEz
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Use reg in module A as the parameter of A's inner module B

Sorry but I had to change the question because I found the example I gave before is very vague. So I wrote this code below in purpose of getting the last 7 digits of a binary number "a". Then display them as binary to the console. But I failed and…
Ling
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Verilog. Trying to expand Datapath and Decoder with 3-AluControl bits for multiplication and bltz MIPS instructions

I currently am doing a assignment for my university on verilog, where we need to implement a single-cycle MIPS processor. Issue is, we are only given 3 Control-Bits on the ALU, just my group has no idea how to implement the multiplication and the…
Mark Lauer
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Why do I get Syntax Error in Assignment statement l-value?

I cannot find the syntax error in this code of a MIPS decoder. I am currently inside of the default case, and it gives me the errors Decoder.v:104: syntax error. Decoder.v:106: Syntax in assignment statement l-value Here is the code: module…
Mark Lauer
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