Syntax checking with iverilog

Question

I want to run iverilog just to check syntax in my file. I don't want it to actually compile anything since I'm working on a large codebase and don't want to find and "include" all included files.

`include "header.vh"   // not a file in current dir so iverilog can't find it

module test;
input a;
input b;
output c;

assign c = a & b   // missed a semicolon - wanna use iverilog to tell me this

assign d = a + XMR.TO.ANOTHER.MODULE.d;    // Want iverilog to ignore the XMR and move on since there's no syntax issue here

// no endmodule - should also be reported by iverilog

Command I tried:

iverilog -t null -Wall test.v

Please help me find a solution... even if you could point me to a different tool, that'd be great.

what did iverilog tell you? what is wrong with it? – Serge Aug 18 '19 at 01:09 — Serge, Aug 18 '19 at 01:09

score 2 · Answer 1 · answered Aug 18 '19 at 04:43

You should only use `include to include files that are required for compilation of the code that follows. Verilog does not require modules that are cross-referenced to be compiled first.

Instead, give the compiler a list of files to compile. Then you should be able to use any tool to compile just one of the files and get the syntax errors you are searching for.

Syntax checking with iverilog

1 Answers1